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preliminary fme-mb96380 rev 8 fujitsu semiconductor data sheet 2008-2-4 16-bit proprietary microcontroller cmos f 2 mc-16fx mb96380 series mb96384 *1 /385 *1 mb96 f385 *1 /f386/f387 /f388 *1 /f389 *1 description mb96380 series is based on fujitsus advanced 16fx architecture (16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series enabling thus easy migration of 16lx software to the new 16fx products. in comparison with the previous generation, the 16fx products include signi?antly improved performance even at the same operation frequency, a reduced power consumption and a faster start-up time. for highest processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 56mhz operation frequency from an external 4mhz resonator. the result is a minimum instruction cycle time of 17.8ns going together with excellent emi behavior. an on-chip clock modulation circuit signi?antly reduces emission peaks in the frequency spectrum. the emitted power is minimized by the on-chip voltage regulator that reduces the internal cpu voltage. a ?xible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed. *1: these devices are under development. all information in this datasheet is preliminary for the devices under development.
preliminary mb96380 series fme-mb96380 rev 8 2 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 3 features feature description technology 0.18 m cmos cpu f2mc-16fx cpu up to 56 mhz internal, 17.8 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1..25, x1 when pll stop) 3-16 mhz external quartz clock up to 56 mhz external clock for devices with fast clock input feature 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and safe startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (part number suffix ?? and on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regula- tor internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support dma automatic transfer function independent of cpu, can be assigned freely to resources interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers three independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer
preliminary mb96380 series fme-mb96380 rev 8 4 2008-2-4 can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i2c up to 400 kbit/s master and slave functionality, 8-bit and 10-bit addressing a/d converter sar-type 10-bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer a/d converter refer- ence voltage switch 2 independent positive a/d converter reference voltages available reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. feature description
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 5 programmable pulse generator 16-bit down counter, cycle and duty setting registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer overflow as clock input can be triggered by software or reload timer stepper motor control- ler stepper motor controller with integrated high current output drivers four high current outputs for each channel two synchronized 8/10-bit pwms per channel internal prescaling for pwm clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock separate power supply for high current output drivers lcd controller lcd controller with up to 4 com 65 seg internal or external voltage generation duty cycle: selectable from options: 1/2, 1/3 and 1/4 fixed 1/3 bias programmable frame period clock source selectable from three options (peripheral clock, subclock or rc oscillator clock) on-chip drivers for internal divider resistors or external divider resistors on-chip data memory for display lcd display can be operated in timer mode blank display: selectable all seg, com and v pins can be switched between general and specialized purposes external divided resistors can be also used to shut off the current when lcd is deactivated sound generator 8-bit pwm signal is mixed with tone frequency from 16-bit reload counter pwm clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock tone frequency: pwm frequency / 2 / (reload value + 1) real time clock can be clocked either from sub oscillator (devices with part number suffix ??, main oscillator or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) read/write accessible second/minute/hour registers can signal interrupts every half second/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock feature description
preliminary mb96380 series fme-mb96380 rev 8 6 2008-2-4 external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0. external bus interface 8-bit or 16-bit bidirectional data up to 24-bit addresses 6 chip select signals multiplexed address/data lines non-multiplexed address/data lines wait state request external bus master possible timing programmable alarm comparators monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds threshold voltages defined externally or generated internally status is readable, interrupts can be masked separately i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels (automotive / cmos-schmitt trigger / ttl) bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization package 120-pin plastic lqfp flash memory supports automatic programming, embedded algorithm tm*1 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles: 10,000 times data retention time: 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase feature description
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 7 *1 : embedded algorithm is a trade mark of advanced micro devices inc.
preliminary mb96380 series fme-mb96380 rev 8 8 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 9 product lineup features mb96v300b mb9638x product type evaluation sample flash product: mb96f38x mask rom product: mb9638x product options ys na lvd persistently on / single clock devices rs lvd can be disabled / single clock devices yw lvd persistently on / dual clock devices rw lvd can be disabled / dual clock devices ts 32kb data flash / lvd persistently on / single clock devices hs 32kb data flash / lvd can be disabled / single clock devices tw 32kb data flash / lvd persistently on / dual clock devices hw 32kb data flash / lvd can be disabled / dual clock devices flash/rom ram 128kb 6kb rom/flash memory emulation by external ram, 92kb internal ram mb96384y *1 , mb96384r *1 160kb 8kb mb96385y *1 , mb96385r *1 , mb96f385y *1 , mb96f385r *1 288kb 16kb mb96f386y, mb96f386r 416kb 16kb mb96f387y, mb96f387r 576kb [flash a: 544kb, flash b (data flash): 32kb] 28kb mb96f388t *1 , mb96f388h *1 832kb [flash a: 544kb, flash b: 288kb] 32kb mb96f389y *1 , mb96f389r *1 , package bga416 fpt-120p-m21 dma 16 channels 7 channels usart 10 channels 5 channels i2c 2 channels 1 channel a/d converter 40 channels 16 channels a/d converter reference voltage switch yes only for mb96f386y, mb96f386r, mb96f387y, mb96f387r 16-bit reload timer 6 channels + 1 channel (for ppg) 4 channels + 1 channel (for ppg) 16-bit free-running timer 4 channels 2 channels 16-bit output compare 12 channels 4 channels
preliminary mb96380 series fme-mb96380 rev 8 10 2008-2-4 *1: these devices are under development. all information in this datasheet is preliminary for the devices under development. 16-bit input capture 12 channels 8 channels 16-bit programmable pulse generator 20 channels 8 channels can interface 5 channels 2 channels mb96384y *1 , mb96384r *1 , mb96(f)385y *1 , mb96(f)385r *1 ,: 1 channel stepping motor controller 6 channels 5 channels external interrupts 16 channels 8 channels non-maskable interrupt 1 channel sound generator 2 channels 2 channels lcd controller 4 com x 72 seg 4 com x 65 seg real time clock 1 i/o ports 136 94 for part number with suf? "w", 96 for part number with suf? "s" alarm comparator 2 channels 2 channels mb96384y *1 , mb96384r *1 , mb96(f)385y *1 , mb96(f)385r *1 ,: 1 channel external bus interface yes chip select 6 signals clock output function 2 channels low voltage reset yes on-chip rc-oscillator yes features mb96v300b mb9638x
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 11 block diagrams block diagram of mb96(f)38x 5 ch. pwm1m0 ... pwm1m4 pwm1p0 ... pwm1p4 pwm2m0 ... pwm2m4 pwm2p0 ... pwm2p4 dv cc dv ss dma controller boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) usart 5 ch. 10-bit adc 16 ch. alarm comparator 2 ch. 3) can interface 2 ch. 3) external interrupt sound generator lcd driver real time clock controller/ watchdog ram voltage regulator sin0...sin2,sin4,sin5 sot0...sot2,sot4,sot5 sck0...sck2,sck4,sck5 alarm0 alarm1 3) wot sgo0, sgo1, sgo0_r, sgo1_r sga0, sga1, sga0_r, sga1_r av cc av ss avrh avrl/avrh2 4) an0 ... an15 adtg frck0 frck0_r int0 ... int7 v0 ... v3 com0 ... com3 seg0 ... seg64 tx0, tx1 3) rx0, rx1 3) peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c stepper motor controller i/o timer 1 icu 4/5/6/7 frck1 in6 ... in7 2 ch. 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit ad00 ... ad15 a00 ... a23 ale rdx wr(l)x, wrhx hrq hakx rdy eclk external bus interface lbx, ubx cs0 ... cs5, cs3_r nmi ckot0, ckot1, ckot1_r ckotx0, ckotx1, ckotx1_r x0, x1 x0a, x1a 1) rstx md0...md2 i2c 1 ch. sda0 scl0 16-bit reload timer 4 ch. tin2_r tin0 ... tin3 tot1_r, tot2_r tot0 ... tot3 i/o timer 0 icu 0/1/2/3 ocu 0/1/2/3 in0, in1 in0_r ... in3_r out0 ... out3 out0_r...out3_r int1_r ... int7_r in4_r ... in7_r 1) x0a/x1a only available on devices with suf? ? flash memory b 2) 2) flash b only available on mb96f388 and mb96f389 3) can1 and alarm1 not available on mb96384 and mb96(f)385 4) avrh2 only available on mb96f386 and mb96f387 16-bit ppg 8 ch. rlt6 ppg0 ... ppg7 ttg0 ... ttg7 ppg0_r ... ppg5_r
preliminary mb96380 series fme-mb96380 rev 8 12 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 13 pin assignments pin assignment of mb96(f)38x lqfp - 120 package code (mold) fpt-120p-m21 (fpt-120p-m21) 89 12345 7 6 101112131415161718192021222324252627282930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 91 92 93 94 95 96 97 98 99 vss p00_3/int6_r/a00/cs3_r/seg15 p00_4/int7_r/ale/seg16 p00_5/ttg2/ttg6/in6/rdx/seg17 p00_6/ttg3/in7/wr(l)x/ttg7/seg18 p00_7/sgo0/eclk/seg19 p01_0/sga0/ad00/seg20 p01_1/out0/ckot1/ad01/seg21 p01_2/out1/ckotx1/ad02/seg22 p01_3/ppg5/ad03/seg23 p01_4/ad04/sin4/seg24 p01_5/ad05/sot4/seg25 p01_6/ad06/sck4/seg26 p01_7/ckotx1_r/ad07/seg27 p02_0/ckot1_r/ad08/seg28 p02_1/in6_r/ad09/seg29 p02_2/in7_r/ad10/seg30 p02_3/sgo0_r/ad11/seg31 p02_4/sga0_r/ad12/seg32 p02_5/out0_r/ad13/seg33 p02_6/out1_r/ad14/seg34 p02_7/ppg5_r/ad15/seg35 p03_0/v0/a16/seg36 p03_1/v1/a17/seg37 p03_2/v2/a18/seg38 p03_3/v3/a19/seg39 p03_4/int4/rx0 p03_5/tx0 p03_6/nmi/int0 vcc vss c p03_7/int1/sin1/cs0/a20/seg40 p13_0/int2/sot1/cs1/a21/seg41 p13_1/int3/sck1/cs2/a22/seg42 p13_2/ppg0/tin0/frck1/cs3/a23/seg43 p13_3/ppg1/tot0/wot/ubx/seg44 p13_4/sin0/int6/seg45 p13_5/sot0/adtg/int7/seg46 p13_6/sck0/ckotx0/lbx/seg47 p13_7/ppg2/ckot0/cs4/seg48 p04_4/ppg3/sda0 p04_5/ppg4/scl0 p06_0/an0/sck5/in2_r/seg49 p06_1/an1/sot5/in3_r/seg50 p06_2/an2/int5/sin5/seg51 p06_3/an3/frck0/seg52 p06_4/an4/in0/ttg0/ttg4/seg53 p06_5/an5/in1/ttg1/ttg5/seg54 p06_6/an6/tin1/in4_r/seg55 p06_7/an7/tot1//in5_r/seg56 avcc avrh avrl/avrh2 avss p05_0/an8/alarm0/seg57 p05_1/an9/alarm1/seg58 p05_2/an10/out2/sgo1/seg59 p05_3/an11/out3/sga1/seg60 vcc vcc p10_3/pwm2m4/ppg7 p10_2/pwm2p4/sck2/ppg6 p10_1/pwm1m4/sot2/tot3 p10_0/pwm1p4/sin2/tin3 dvss dvcc p09_6/pwm2p3 p09_7/pwm2m3 p09_5/pwm1m3 p09_4/pwm1p3 p09_3/pwm2m2 p09_2/pwm2p2 p09_1/pwm1m2 p09_0/pwm1p2 p08_7/pwm2m1 p08_6/pwm2p1 p08_5/pwm1m1 dvss dvcc p08_4/pwm1p1 p08_3/pwm2m0 p08_2/pwm2p0 p08_1/pwm1m0 p08_0/pwm1p0 p05_7/an15/tot2/sga1_r/seg64 p05_6/an14/tin2/sgo1_r/seg63 p05_5/an13/tx1/seg62 p05_4/an12/rx1/int2_r/seg61 vss vcc p00_2/int5_r/rdy/seg14 p00_1/int4_r/wrhx/seg13 p00_0/int3_r/hakx/seg12 p12_7/int1_r/hrq/seg11 p12_6/tot2_r/a15/seg10 p12_5/tin2_r/a14/seg9 p12_4/out3_r/a13/seg8 p12_3/out2_r/a12/seg7 p12_2/tot1_r/a11/seg6 p12_1/tin1_r/a10/seg5 p12_0/in1_r/a09/seg4 p11_7/in0_r/a08/seg3 p11_6/frck0_r/a07/seg2 p11_5/ppg4_r/a06/seg1 p11_4/ppg3_r/a05/seg0 p11_3/ppg2_r/a04/com3 p11_2/ppg1_r/a03/com2 p11_1/ppg0_r/a02/com1 p11_0/a01/com0/cs5 rstx x1a/p04_1 1) x0a/p04_0 1) vss x1 x0 md2 md1 md0 vss 3) 3) 4) 2) 2) alarm1 not available on mb96384 and mb96(f)385 1) devices with suf? w: x0a/x1a devices with suf? s: p04_0, p04_1 3) tx1 resp. rx1 not available on mb96384 and mb96(f)385 4) avrh2 only available on mb96f386 and mb96f387
preliminary mb96380 series fme-mb96380 rev 8 14 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 15 pin function description pin function description (1 / 3) pin name feature description adn external bus external bus interface (non multiplexed mode) data input/ output. external bus interface (multiplexed mode) address output and data input/output adtg adc a/d converter trigger input alarmn alarm comparator alarm comparator n input ale external bus external bus address latch enable output an external bus external bus non-multiplexed address output ann adc a/d converter channel n input av cc supply analog circuits power supply avrh adc a/d converter high reference voltage input avrh2 adc alternative a/d converter high reference voltage input avrl adc a/d converter low reference voltage input av ss supply analog circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output ckotn_r clock output function relocated clock output function n output ckotxn clock output function clock output function n inverted output ckotxn_r clock output function relocated clock output function n inverted output comn lcd lcd com pins eclk external bus external bus clock output csn external bus external bus chip select n output csn_r external bus relocated external bus chip select n output dv cc supply smc pins power supply frckn free running timer free running timer n input frckn_r free running timer relocated free running timer n input hakx external bus external bus hold acknowledge hrq external bus external bus hold request inn icu input capture unit n input inn_r icu relocated input capture unit n input intn external interrupt external interrupt n input
preliminary mb96380 series fme-mb96380 rev 8 16 2008-2-4 intn_r external interrupt relocated external interrupt n input lbx external bus external bus interface lower byte select strobe output mdn core input pins for specifying the operating mode. nmi external interrupt non-maskable interrupt input outn ocu output compare unit n waveform output outn_r ocu relocated output compare unit n waveform output pxx_n gpio general purpose io ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmable pulse generator n output pwmn smc smc pwm high current rdx external bus external bus interface read strobe output rdy external bus external bus interface external wait state request input rstx core reset input rxn can can interface n rx input sckn usart usart n serial clock input/output scln i2c i2c interface n clock i/o input/output sdan i2c i2c interface n serial data i/o input/output segn lcd lcd segment n sga sound generator sg amplitude output sgo sound generator sg sound/tone output sga_r sound generator relocated sg amplitude output sgo_r sound generator relocated sg sound/tone output sinn usart usart n serial data input sotn usart usart n serial data output tinn reload timer reload timer n event input tinn_r reload timer relocated reload timer n event input totn reload timer reload timer n output totn_r reload timer relocated reload timer n output ttgn ppg programmable pulse generator n trigger input txn can can interface n tx output pin function description (2 / 3) pin name feature description
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 17 ubx external bus external bus interface upper byte select strobe output vn lcd lcd voltage references v cc supply power supply v ss supply power supply wot rtc real timer clock output wrhx external bus external bus high byte write strobe output wrlx/wrx external bus external bus low byte / word write strobe output x0 clock oscillator input x0a clock subclock oscillator input (only for devices with suf? "w") x1 clock oscillator output x1a clock subclock oscillator output (only for devices with suf? "w") pin function description (3 / 3) pin name feature description
preliminary mb96380 series fme-mb96380 rev 8 18 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 19 pin circuit type fpt-120p-m21 pin no. circuit type 1 supply 2f 3 to 11 j 12,13 n 14 to 21 k 22 supply 23 to 24 g 25 supply 26 to 29 k 30,31 supply 32 to 35 k 36 to 40 m 41,42 supply 43 to 52 m 53,54 supply 55 to 59 m 60, 61 supply 62 to 64 c 65, 66 a 67 supply 68,69 b 1) 68,69 h 2) 70 e 71 to 89 j 90 to 91 supply 1) devices with suf? ? 2) devices without suf? ?
preliminary mb96380 series fme-mb96380 rev 8 20 2008-2-4 92 to 112 j 113 to 116 l 117 to 119 h 120 supply fpt-120p-m21 pin no. circuit type 1) devices with suf? ? 2) devices without suf? ?
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 21 i/o circuit type type circuit remarks a high-speed oscillation circuit: programmable between oscillation mode (ex- ternal crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) programmable feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode b low-speed oscillation circuit: programmable feedback resistor = approx. 2*5m ? . feedback resistor is grounded in the center when the oscillator is disabled c mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? x1 x0 r r mrfbe xout fci 0 1 fci or osc disable x1a x0a r r srfbe xout osc disable r hysteresis inputs r pull-up resistor hysteresis inputs
preliminary mb96380 series fme-mb96380 rev 8 22 2008-2-4 f power supply input protection circuit g a/d converter ref+ (avrh/avrh2) power sup- ply input pin with protection circuit flash devices do not have a protection circuit against vcc for pins avrh/avrh2 devices without avrh reference switch do not have an analog switch for the avrl pin h cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 23 j cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. seg or com output k cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function. programmable pull-up resistor: 50k ? approx. analog input seg output type circuit remarks pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input seg, com output standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input seg output analog input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96380 series fme-mb96380 rev 8 24 2008-2-4 l cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. analog input vx input seg output m cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma, i ol = 30ma, i oh = -30ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks standby control for input shutdown pout pull-up control nout r hysteresis input hysteresis input seg output analog input standby control for input shutdown standby control for input shutdown standby control for input shutdown vx input ttl input automotive input pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 25 n cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. type circuit remarks pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown
preliminary mb96380 series fme-mb96380 rev 8 26 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 27 memory map mb96v300b mb96(f)3xx ff:ffff h emulation rom user rom / external bus *4 de:0000 h external bus external bus 10:0000 h 0f:e000 h boot-rom boot-rom reserved reserved 0e:0000 h external ram 02:0000 h internal ram bank 1 reserved ramend1 *2 internal ram bank 1 ram availability de- pending on the device ramstart1 2 01:0000 h reserved rom/ram mirror rom/ram mirror 00:8000 h internal ram bank 0 internal ram bank 0 ramstart0 *2 reserved ramstart0 *3 external bus external bus end address *2 00:0c00 h external bus peripherals peripherals 00:0380 h 00:0180 h gpr *1 gpr *1 00:0100 h dma dma 00:00f0 h external bus external bus 00:0000 h peripheral peripheral *1: unused gpr banks can be used as ram area *2: for external bus end address and ramstart/end addresses, please refer to the table on the next page. *3: for eva device, ramstart0 depends on the con?uration of the emulated device. *4: for details about user rom area, see the user rom memory map on the following pages. the external bus area and dma area are only available if the device contains the corresponding resource. the available ram and rom area depends on the device.
preliminary mb96380 series fme-mb96380 rev 8 28 2008-2-4 ramstart/end and external bus end addresses devices bank 0 ram size bank 1 ram size external bus end address ramstart0 ramstart1 ramend1 mb96384 6kb - 00:61ff h 00:6a40 h -- mb96385/f385 8kb - 00:61ff h 00:6240 h -- mb96f386, mb96f387 16kb - 00:41ff h 00:4240 h -- mb96f388 28kb - 00:11ff h 00:1240 h -- mb96f389 28kb 4kb 00:11ff h 00:1240 h 01:8000 h 01:8fff h
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 29 user rom memory map for flash devices mb96f385r mb96f386r mb96f387r mb96f385y mb96f386y mb96f387y alternative mode cpu address flash memory mode address flash size 160kbyte flash size 288kbyte flash size 416kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k s39 - 64k s39 - 64k flash a fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h s38 - 64k s38 - 64k s38 - 64k fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h external bus s37 - 64k s37 - 64k fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h s36 - 64k s36 - 64k fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h external bus s35 - 64k fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h s34 - 64k f9:ffff h f9:0000 h 39:ffff h 39:0000 h external bus f8:ffff h f8:0000 h 38:ffff h 38:0000 h f7:ffff h f7:0000 h 37:ffff h 37:0000 h f6:ffff h f6:0000 h 36:ffff h 36:0000 h f5:ffff h f5:0000 h 35:ffff h 35:0000 h f4:ffff h f4:0000 h 34:ffff h 34:0000 h f3:ffff h f3:0000 h 33:ffff h 33:0000 h f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h reserved reserved reserved df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k sa3 - 8k sa3 - 8k flash a df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k sa2 - 8k sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k sa1 - 8k sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 sa0 - 8k *1 sa0 - 8k *1 de:ffff h de:0000 h reserved reserved reserved *1: sector sa0 contains the rom con?uration block rcba at cpu address df:0000 h - df:007f h
preliminary mb96380 series fme-mb96380 rev 8 30 2008-2-4 mb96f388t mb96f389r mb96f388h mb96f389y alternative mode cpu address flash memory mode address flash size 576kbyte flash size 832kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k s39 - 64k fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h s38 - 64k s38 - 64k flash a fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h s37 - 64k s37 - 64k fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h s36 - 64k s36 - 64k fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h s35 - 64k s35 - 64k fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h s34 - 64k s34 - 64k f9:ffff h f9:0000 h 39:ffff h 39:0000 h s33 - 64k s33 - 64k f8:ffff h f8:0000 h 38:ffff h 38:0000 h s32 - 64k s32 - 64k f7:ffff h f7:0000 h 37:ffff h 37:0000 h external bus s31 - 64k flash b f6:ffff h f6:0000 h 36:ffff h 36:0000 h s30 - 64k f5:ffff h f5:0000 h 35:ffff h 35:0000 h s29 - 64k f4:ffff h f4:0000 h 34:ffff h 34:0000 h s28 - 64k f3:ffff h f3:0000 h 33:ffff h 33:0000 h external bus f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h reserved reserved df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k sa3 - 8k flash a df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 sa0 - 8k *1 de:ffff h de:8000 h reserved reserved de:7fff h de:6000 h 1e:7fff h 1e:6000 h sb3 - 8k sb3 - 8k flash b de:5fff h de:4000 h 1e:5fff h 1e:4000 h sb2 - 8k sb2 - 8k de:3fff h de:2000 h 1e:3fff h 1e:2000 h sb1 - 8k sb1 - 8k de:1fff h de:0000 h 1e:1fff h 1e:0000 h sb0 - 8k *2 sb0 - 8k *2 *1: sector sa0 contains the rom con?uration block rcba at cpu address df:0000 h - df:007f h *2: sector sb0 contains the rom con?uration block rcbb at cpu address de:0000 h - de:002f h
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 31 user rom memory map for mask rom devices mb96384 mb96385 cpu address rom size 128kbyte rom size 160kbyte ff:ffff h ff:0000 h 128k rom 128k rom fe:ffff h fe:0000 h fd:ffff h e0:0000 h external bus external bus df:ffff h df:8000 h reserved reserved df:7fff h df:0080 h 32k rom df:007f h df:0000 h rom con?uration block rcb rom con?uration block rcb de:ffff h de:0000 h reserved reserved
preliminary mb96380 series fme-mb96380 rev 8 32 2008-2-4 serial programming communication interface note: for handshaking pin, please use for these devices the default port p00_1 on pin 88. if any other pin is required, please contact the flash programmer device vendor. usart pins for flash serial programming (md[2:0] = 010, serial communication mode) mb96f38x pin number usart number normal function lqfp-120 8 usart0 sin0 9sot0 10 sck0 3 usart1 sin1 4sot1 5 sck1 56 usart2 sin2 57 sot2 58 sck2
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 33 i/o map i/o map mb96(f)38x (1 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access 000000h i/o port p00 - port data register pdr00 rw 000001h i/o port p01 - port data register pdr01 rw 000002h i/o port p02 - port data register pdr02 rw 000003h i/o port p03 - port data register pdr03 rw 000004h i/o port p04 - port data register pdr04 rw 000005h i/o port p05 - port data register pdr05 rw 000006h i/o port p06 - port data register pdr06 rw 000007h reserved - 000008h i/o port p08 - port data register pdr08 rw 000009h i/o port p09 - port data register pdr09 rw 00000ah i/o port p10 - port data register pdr10 rw 00000bh i/o port p11 - port data register pdr11 rw 00000ch i/o port p12 - port data register pdr12 rw 00000dh i/o port p13 - port data register pdr13 rw 00000eh- 000017h reserved - 000018h adc0 - control status register low adcsl adcs rw 000019h adc0 - control status register high adcsh rw 00001ah adc0 - data register low adcrl adcr r 00001bh adc0 - data register high adcrh r 00001ch adc0 - setting register adsr rw 00001dh adc0 - setting register rw 00001eh adc0 - extended con?uration register adecr rw 00001fh reserved - 000020h frt0 - data register of free-running timer tcdt0 rw 000021h frt0 - data register of free-running timer rw 000022h frt0 - control status register of free-running timer low tccsl0 tccs0 rw 000023h frt0 - control status register of free-running timer high tccsh0 rw
preliminary mb96380 series fme-mb96380 rev 8 34 2008-2-4 000024h frt1 - data register of free-running timer tcdt1 rw 000025h frt1 - data register of free-running timer rw 000026h frt1 - control status register of free-running timer low tccsl1 tccs1 rw 000027h frt1 - control status register of free-running timer high tccsh1 rw 000028h ocu0 - output compare control status ocs0 rw 000029h ocu1 - output compare control status ocs1 rw 00002ah ocu0 - compare register occp0 rw 00002bh ocu0 - compare register rw 00002ch ocu1 - compare register occp1 rw 00002dh ocu1 - compare register rw 00002eh ocu2 - output compare control status ocs2 rw 00002fh ocu3 - output compare control status ocs3 rw 000030h ocu2 - compare register occp2 rw 000031h ocu2 - compare register rw 000032h ocu3 - compare register occp3 rw 000033h ocu3 - compare register rw 000034h- 00003fh reserved - 000040h icu0/icu1 - control status register ics01 rw 000041h icu0/icu1 - edge register ice01 rw 000042h icu0 - capture register low ipcpl0 ipcp0 r 000043h icu0 - capture register high ipcph0 r 000044h icu1 - capture register low ipcpl1 ipcp1 r 000045h icu1 - capture register high ipcph1 r 000046h icu2/icu3 - control status register ics23 rw 000047h icu2/icu3 - edge register ice23 rw 000048h icu2 - capture register low ipcpl2 ipcp2 r 000049h icu2 - capture register high ipcph2 r 00004ah icu3 - capture register low ipcpl3 ipcp3 r i/o map mb96(f)38x (2 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 35 00004bh icu3 - capture register high ipcph3 r 00004ch icu4/icu5 - control status register ics45 rw 00004dh icu4/icu5 - edge register ice45 rw 00004eh icu4 - capture register low ipcpl4 ipcp4 r 00004fh icu4 - capture register high ipcph4 r 000050h icu5 - capture register low ipcpl5 ipcp5 r 000051h icu5 - capture register high ipcph5 r 000052h icu6/icu7 - control status register ics67 rw 000053h icu6/icu7 - edge register ice67 rw 000054h icu6 - capture register low ipcpl6 ipcp6 r 000055h icu6 - capture register high ipcph6 r 000056h icu7 - capture register low ipcpl7 ipcp7 r 000057h icu7 - capture register high ipcph7 r 000058h extint0 - external interrupt enable register enir0 rw 000059h extint0 - external interrupt interrupt request register eirr0 rw 00005ah extint0 - external interrupt level select low elvrl0 elvr0 rw 00005bh extint0 - external interrupt level select high elvrh0 rw 00005ch- 00005fh reserved - 000060h rlt0 - timer control status register low tmcsrl0 tmcsr0 rw 000061h rlt0 - timer control status register high tmcsrh0 rw 000062h rlt0 - reload register - for writing tmrlr0 w 000062h rlt0 - reload register - for reading tmr0 r 000063h rlt0 - reload register - for writing w 000063h rlt0 - reload register - for reading r 000064h rlt1 - timer control status register low tmcsrl1 tmcsr1 rw 000065h rlt1 - timer control status register high tmcsrh1 rw 000066h rlt1 - reload register - for writing tmrlr1 w 000066h rlt1 - reload register - for reading tmr1 r 000067h rlt1 - reload register - for writing w i/o map mb96(f)38x (3 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 36 2008-2-4 000067h rlt1 - reload register - for reading r 000068h rlt2 - timer control status register low tmcsrl2 tmcsr2 rw 000069h rlt2 - timer control status register high tmcsrh2 rw 00006ah rlt2 - reload register - for writing tmrlr2 w 00006ah rlt2 - reload register - for reading tmr2 r 00006bh rlt2 - reload register - for writing w 00006bh rlt2 - reload register - for reading r 00006ch rlt3 - timer control status register low tmcsrl3 tmcsr3 rw 00006dh rlt3 - timer control status register high tmcsrh3 rw 00006eh rlt3 - reload register - for writing tmrlr3 w 00006eh rlt3 - reload register - for reading tmr3 r 00006fh rlt3 - reload register - for writing w 00006fh rlt3 - reload register - for reading r 000070h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 rw 000071h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 rw 000072h rlt6 - reload register (dedic. rlt for ppg) - for writing tmrlr6 w 000072h rlt6 - reload register (dedic. rlt for ppg) - for reading tmr6 r 000073h rlt6 - reload register (dedic. rlt for ppg) - for writing w 000073h rlt6 - reload register (dedic. rlt for ppg) - for reading r 000074h ppg3-ppg0 - general control register 1 low gcn1l0 gcn10 rw 000075h ppg3-ppg0 - general control register 1 high gcn1h0 rw 000076h ppg3-ppg0 - general control register 2 low gcn2l0 gcn20 rw 000077h ppg3-ppg0 - general control register 2 high gcn2h0 rw 000078h ppg0 - timer register ptmr0 r 000079h ppg0 - timer register r 00007ah ppg0 - period setting register pcsr0 w i/o map mb96(f)38x (4 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 37 00007bh ppg0 - period setting register w 00007ch ppg0 - duty cycle register pdut0 w 00007dh ppg0 - duty cycle register w 00007eh ppg0 - control status register low pcnl0 pcn0 rw 00007fh ppg0 - control status register high pcnh0 rw 000080h ppg1 - timer register ptmr1 r 000081h ppg1 - timer register r 000082h ppg1 - period setting register pcsr1 w 000083h ppg1 - period setting register w 000084h ppg1 - duty cycle register pdut1 w 000085h ppg1 - duty cycle register w 000086h ppg1 - control status register low pcnl1 pcn1 rw 000087h ppg1 - control status register high pcnh1 rw 000088h ppg2 - timer register ptmr2 r 000089h ppg2 - timer register r 00008ah ppg2 - period setting register pcsr2 w 00008bh ppg2 - period setting register w 00008ch ppg2 - duty cycle register pdut2 w 00008dh ppg2 - duty cycle register w 00008eh ppg2 - control status register low pcnl2 pcn2 rw 00008fh ppg2 - control status register high pcnh2 rw 000090h ppg3 - timer register ptmr3 r 000091h ppg3 - timer register r 000092h ppg3 - period setting register pcsr3 w 000093h ppg3 - period setting register w 000094h ppg3 - duty cycle register pdut3 w 000095h ppg3 - duty cycle register w 000096h ppg3 - control status register low pcnl3 pcn3 rw 000097h ppg3 - control status register high pcnh3 rw 000098h ppg7-ppg4 - general control register 1 low gcn1l1 gcn11 rw i/o map mb96(f)38x (5 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 38 2008-2-4 000099h ppg7-ppg4 - general control register 1 high gcn1h1 rw 00009ah ppg7-ppg4 - general control register 2 low gcn2l1 gcn21 rw 00009bh ppg7-ppg4 - general control register 2 high gcn2h1 rw 00009ch ppg4 - timer register ptmr4 r 00009dh ppg4 - timer register r 00009eh ppg4 - period setting register pcsr4 w 00009fh ppg4 - period setting register w 0000a0h ppg4 - duty cycle register pdut4 w 0000a1h ppg4 - duty cycle register w 0000a2h ppg4 - control status register low pcnl4 pcn4 rw 0000a3h ppg4 - control status register high pcnh4 rw 0000a4h ppg5 - timer register ptmr5 r 0000a5h ppg5 - timer register r 0000a6h ppg5 - period setting register pcsr5 w 0000a7h ppg5 - period setting register w 0000a8h ppg5 - duty cycle register pdut5 w 0000a9h ppg5 - duty cycle register w 0000aah ppg5 - control status register low pcnl5 pcn5 rw 0000abh ppg5 - control status register high pcnh5 rw 0000ach i2c0 - bus status register ibsr0 r 0000adh i2c0 - bus control register ibcr0 rw 0000aeh i2c0 - ten bit slave address register low itbal0 itba0 rw 0000afh i2c0 - ten bit slave address register high itbah0 rw 0000b0h i2c0 - ten bit address mask register low itmkl0 itmk0 rw 0000b1h i2c0 - ten bit address mask register high itmkh0 rw 0000b2h i2c0 - seven bit slave address register isba0 rw 0000b3h i2c0 - seven bit address mask register ismk0 rw 0000b4h i2c0 - data register idar0 rw 0000b5h i2c0 - clock control register iccr0 rw i/o map mb96(f)38x (6 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 39 0000b6h- 0000bfh reserved - 0000c0h usart0 - serial mode register smr0 rw 0000c1h usart0 - serial control register scr0 rw 0000c2h usart0 - tx register tdr0 w 0000c2h usart0 - rx register rdr0 r 0000c3h usart0 - serial status ssr0 rw 0000c4h usart0 - control/com. register eccr0 rw 0000c5h usart0 - ext. status register escr0 rw 0000c6h usart0 - baud rate generator register low bgrl0 bgr0 rw 0000c7h usart0 - baud rate generator register high bgrh0 rw 0000c8h usart0 - extended serial interrupt register esir0 rw 0000c9h reserved - 0000cah usart1 - serial mode register smr1 rw 0000cbh usart1 - serial control register scr1 rw 0000cch usart1 - tx register tdr1 w 0000cch usart1 - rx register rdr1 r 0000cdh usart1 - serial status ssr1 rw 0000ceh usart1 - control/com. register eccr1 rw 0000cfh usart1 - ext. status register escr1 rw 0000d0h usart1 - baud rate generator register low bgrl1 bgr1 rw 0000d1h usart1 - baud rate generator register high bgrh1 rw 0000d2h usart1 - extended serial interrupt register esir1 rw 0000d3h reserved - 0000d4h usart2 - serial mode register smr2 rw 0000d5h usart2 - serial control register scr2 rw 0000d6h usart2 - tx register tdr2 w 0000d6h usart2 - rx register rdr2 r 0000d7h usart2 - serial status ssr2 rw 0000d8h usart2 - control/com. register eccr2 rw i/o map mb96(f)38x (7 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 40 2008-2-4 0000d9h usart2 - ext. status register escr2 rw 0000dah usart2 - baud rate generator register low bgrl2 bgr2 rw 0000dbh usart2 - baud rate generator register high bgrh2 rw 0000dch usart2 - extended serial interrupt register esir2 rw 0000ddh- 0000efh reserved - 0000f0h- 0000ffh external bus area extbus0 rw 000100h dma0 - buffer address pointer low byte bapl0 rw 000101h dma0 - buffer address pointer middle byte bapm0 rw 000102h dma0 - buffer address pointer high byte baph0 rw 000103h dma0 - dma control register dmacs0 rw 000104h dma0 - i/o register address pointer low byte ioal0 ioa0 rw 000105h dma0 - i/o register address pointer high byte ioah0 rw 000106h dma0 - data counter low byte dctl0 dct0 rw 000107h dma0 - data counter high byte dcth0 rw 000108h dma1 - buffer address pointer low byte bapl1 rw 000109h dma1 - buffer address pointer middle byte bapm1 rw 00010ah dma1 - buffer address pointer high byte baph1 rw 00010bh dma1 - dma control register dmacs1 rw 00010ch dma1 - i/o register address pointer low byte ioal1 ioa1 rw 00010dh dma1 - i/o register address pointer high byte ioah1 rw 00010eh dma1 - data counter low byte dctl1 dct1 rw 00010fh dma1 - data counter high byte dcth1 rw 000110h dma2 - buffer address pointer low byte bapl2 rw 000111h dma2 - buffer address pointer middle byte bapm2 rw 000112h dma2 - buffer address pointer high byte baph2 rw 000113h dma2 - dma control register dmacs2 rw 000114h dma2 - i/o register address pointer low byte ioal2 ioa2 rw 000115h dma2 - i/o register address pointer high byte ioah2 rw 000116h dma2 - data counter low byte dctl2 dct2 rw i/o map mb96(f)38x (8 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 41 000117h dma2 - data counter high byte dcth2 rw 000118h dma3 - buffer address pointer low byte bapl3 rw 000119h dma3 - buffer address pointer middle byte bapm3 rw 00011ah dma3 - buffer address pointer high byte baph3 rw 00011bh dma3 - dma control register dmacs3 rw 00011ch dma3 - i/o register address pointer low byte ioal3 ioa3 rw 00011dh dma3 - i/o register address pointer high byte ioah3 rw 00011eh dma3 - data counter low byte dctl3 dct3 rw 00011fh dma3 - data counter high byte dcth3 rw 000120h dma4 - buffer address pointer low byte bapl4 rw 000121h dma4 - buffer address pointer middle byte bapm4 rw 000122h dma4 - buffer address pointer high byte baph4 rw 000123h dma4 - dma control register dmacs4 rw 000124h dma4 - i/o register address pointer low byte ioal4 ioa4 rw 000125h dma4 - i/o register address pointer high byte ioah4 rw 000126h dma4 - data counter low byte dctl4 dct4 rw 000127h dma4 - data counter high byte dcth4 rw 000128h dma5 - buffer address pointer low byte bapl5 rw 000129h dma5 - buffer address pointer middle byte bapm5 rw 00012ah dma5 - buffer address pointer high byte baph5 rw 00012bh dma5 - dma control register dmacs5 rw 00012ch dma5 - i/o register address pointer low byte ioal5 ioa5 rw 00012dh dma5 - i/o register address pointer high byte ioah5 rw 00012eh dma5 - data counter low byte dctl5 dct5 rw 00012fh dma5 - data counter high byte dcth5 rw 000130h dma6 - buffer address pointer low byte bapl6 rw 000131h dma6 - buffer address pointer middle byte bapm6 rw 000132h dma6 - buffer address pointer high byte baph6 rw 000133h dma6 - dma control register dmacs6 rw 000134h dma6 - i/o register address pointer low byte ioal6 ioa6 rw i/o map mb96(f)38x (9 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 42 2008-2-4 000135h dma6 - i/o register address pointer high byte ioah6 rw 000136h dma6 - data counter low byte dctl6 dct6 rw 000137h dma6 - data counter high byte dcth6 rw 000138h- 00017fh reserved - 000180h- 00037fh cpu - general purpose registers (ram access) gpr_ram rw 000380h dma0 - interrupt select disel0 rw 000381h dma1 - interrupt select disel1 rw 000382h dma2 - interrupt select disel2 rw 000383h dma3 - interrupt select disel3 rw 000384h dma4 - interrupt select disel4 rw 000385h dma5 - interrupt select disel5 rw 000386h dma6 - interrupt select disel6 rw 000387h- 00038fh reserved - 000390h dma7-dma0 - status register low dsrl dsr rw 000391h dma15-dma8 - status register high dsrh rw 000392h dma7-dma0 - stop status register low dssrl dssr rw 000393h dma15-dma8 - stop status register high dssrh rw 000394h dma7-dma0 - enable register low derl der rw 000395h dma15-dma8 enable register high derh rw 000396h- 00039fh reserved - 0003a0h interrupt level register ilr icr rw 0003a1h interrupt index register idx rw 0003a2h interrupt vector table base register low tbrl tbr rw 0003a3h interrupt vector table base register high tbrh rw 0003a4h delayed interrupt register dirr rw 0003a5h non maskable interrupt register nmi rw 0003a6h- 0003abh reserved - i/o map mb96(f)38x (10 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 43 0003ach edsu communication interrupt selection low edsu2l edsu2 rw 0003adh edsu communication interrupt selection high edsu2h rw 0003aeh rom mirror control register romm rw 0003afh edsu con?uration register edsu rw 0003b0h memory patch control/status register ch 0/1 pfcs0 rw 0003b1h memory patch control/status register ch 0/1 rw 0003b2h memory patch control/status register ch 2/3 pfcs1 rw 0003b3h memory patch control/status register ch 2/3 rw 0003b4h memory patch control/status register ch 4/5 pfcs2 rw 0003b5h memory patch control/status register ch 4/5 rw 0003b6h memory patch control/status register ch 6/7 pfcs3 rw 0003b7h memory patch control/status register ch 6/7 rw 0003b8h memory patch function - patch address 0 low pfal0 rw 0003b9h memory patch function - patch address 0 middle pfam0 rw 0003bah memory patch function - patch address 0 high pfah0 rw 0003bbh memory patch function - patch address 1 low pfal1 rw 0003bch memory patch function - patch address 1 middle pfam1 rw 0003bdh memory patch function - patch address 1 high pfah1 rw 0003beh memory patch function - patch address 2 low pfal2 rw 0003bfh memory patch function - patch address 2 middle pfam2 rw 0003c0h memory patch function - patch address 2 high pfah2 rw 0003c1h memory patch function - patch address 3 low pfal3 rw 0003c2h memory patch function - patch address 3 middle pfam3 rw 0003c3h memory patch function - patch address 3 high pfah3 rw 0003c4h memory patch function - patch address 4 low pfal4 rw 0003c5h memory patch function - patch address 4 middle pfam4 rw 0003c6h memory patch function - patch address 4 high pfah4 rw 0003c7h memory patch function - patch address 5 low pfal5 rw 0003c8h memory patch function - patch address 5 middle pfam5 rw 0003c9h memory patch function - patch address 5 high pfah5 rw i/o map mb96(f)38x (11 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 44 2008-2-4 0003cah memory patch function - patch address 6 low pfal6 rw 0003cbh memory patch function - patch address 6 middle pfam6 rw 0003cch memory patch function - patch address 6 high pfah6 rw 0003cdh memory patch function - patch address 7 low pfal7 rw 0003ceh memory patch function - patch address 7 middle pfam7 rw 0003cfh memory patch function - patch address 7 high pfah7 rw 0003d0h memory patch function - patch data 0 low pfdl0 pfd0 rw 0003d1h memory patch function - patch data 0 high pfdh0 rw 0003d2h memory patch function - patch data 1 low pfdl1 pfd1 rw 0003d3h memory patch function - patch data 1 high pfdh1 rw 0003d4h memory patch function - patch data 2 low pfdl2 pfd2 rw 0003d5h memory patch function - patch data 2 high pfdh2 rw 0003d6h memory patch function - patch data 3 low pfdl3 pfd3 rw 0003d7h memory patch function - patch data 3 high pfdh3 rw 0003d8h memory patch function - patch data 4 low pfdl4 pfd4 rw 0003d9h memory patch function - patch data 4 high pfdh4 rw 0003dah memory patch function - patch data 5 low pfdl5 pfd5 rw 0003dbh memory patch function - patch data 5 high pfdh5 rw 0003dch memory patch function - patch data 6 low pfdl6 pfd6 rw 0003ddh memory patch function - patch data 6 high pfdh6 rw 0003deh memory patch function - patch data 7 low pfdl7 pfd7 rw 0003dfh memory patch function - patch data 7 high pfdh7 rw 0003e0h- 0003f0h reserved - 0003f1h memory control status register a mcsra rw 0003f2h memory timing con?uration register a low mtcral mtcra rw 0003f3h memory timing con?uration register a high mtcrah rw 0003f4h reserved - 0003f5h memory control status register b mcsrb rw 0003f6h memory timing con?uration register b low mtcrbl mtcrb rw i/o map mb96(f)38x (12 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 45 0003f7h memory timing con?uration register b high mtcrbh rw 0003f8h flash memory write control register 0 fmwc0 rw 0003f9h flash memory write control register 1 fmwc1 rw 0003fah flash memory write control register 2 fmwc2 rw 0003fbh flash memory write control register 3 fmwc3 rw 0003fch flash memory write control register 4 fmwc4 rw 0003fdh flash memory write control register 5 fmwc5 rw 0003feh- 0003ffh reserved - 000400h standby mode control register smcr rw 000401h clock select register cksr rw 000402h clock stabilisation select register ckssr rw 000403h clock monitor register ckmr r 000404h clock frequency control register low ckfcrl ckfcr rw 000405h clock frequency control register high ckfcrh rw 000406h pll control register low pllcrl pllcr rw 000407h pll control register high pllcrh rw 000408h rc clock timer control register rctcr rw 000409h main clock timer control register mctcr rw 00040ah sub clock timer control register sctcr rw 00040bh reset cause and clock status register with clear function rccsrc r 00040ch reset con?uration register rcr rw 00040dh reset cause and clock status register rccsr r 00040eh watch dog timer con?uration register wdtc rw 00040fh watch dog timer clear pattern register wdtcp w 000410h- 000414h reserved - 000415h clock output activation register coar rw 000416h clock output con?uration register 0 cocr0 rw 000417h clock output con?uration register 1 cocr1 rw i/o map mb96(f)38x (13 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 46 2008-2-4 000418h clock modulator control register cmcr rw 000419h reserved - 00041ah clock modulator parameter register low cmprl cmpr rw 00041bh clock modulator parameter register high cmprh rw 00041ch- 00042bh reserved - 00042ch voltage regulator control register vrcr rw 00042dh clock input and lvd control register cilcr rw 00042eh- 00042fh reserved - 000430h i/o port p00 - data direction register ddr00 rw 000431h i/o port p01 - data direction register ddr01 rw 000432h i/o port p02 - data direction register ddr02 rw 000433h i/o port p03 - data direction register ddr03 rw 000434h i/o port p04 - data direction register ddr04 rw 000435h i/o port p05 - data direction register ddr05 rw 000436h i/o port p06 - data direction register ddr06 rw 000437h reserved - 000438h i/o port p08 - data direction register ddr08 rw 000439h i/o port p09 - data direction register ddr09 rw 00043ah i/o port p10 - data direction register ddr10 rw 00043bh i/o port p11 - data direction register ddr11 rw 00043ch i/o port p12 - data direction register ddr12 rw 00043dh i/o port p13 - data direction register ddr13 rw 00043eh- 000443h reserved - 000444h i/o port p00 - port input enable register pier00 rw 000445h i/o port p01 - port input enable register pier01 rw 000446h i/o port p02 - port input enable register pier02 rw 000447h i/o port p03 - port input enable register pier03 rw 000448h i/o port p04 - port input enable register pier04 rw i/o map mb96(f)38x (14 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 47 000449h i/o port p05 - port input enable register pier05 rw 00044ah i/o port p06 - port input enable register pier06 rw 00044bh reserved - 00044ch i/o port p08 - port input enable register pier08 rw 00044dh i/o port p09 - port input enable register pier09 rw 00044eh i/o port p10 - port input enable register pier10 rw 00044fh i/o port p11 - port input enable register pier11 rw 000450h i/o port p12 - port input enable register pier12 rw 000451h i/o port p13 - port input enable register pier13 rw 000452h- 000457h reserved - 000458h i/o port p00 - port input level register pilr00 rw 000459h i/o port p01 - port input level register pilr01 rw 00045ah i/o port p02 - port input level register pilr02 rw 00045bh i/o port p03 - port input level register pilr03 rw 00045ch i/o port p04 - port input level register pilr04 rw 00045dh i/o port p05 - port input level register pilr05 rw 00045eh i/o port p06 - port input level register pilr06 rw 00045fh reserved - 000460h i/o port p08 - port input level register pilr08 rw 000461h i/o port p09 - port input level register pilr09 rw 000462h i/o port p10 - port input level register pilr10 rw 000463h i/o port p11 - port input level register pilr11 rw 000464h i/o port p12 - port input level register pilr12 rw 000465h i/o port p13 - port input level register pilr13 rw 000466h- 00046bh reserved - 00046ch i/o port p00 - extended port input level register epilr00 rw 00046dh i/o port p01 - extended port input level register epilr01 rw 00046eh i/o port p02 - extended port input level register epilr02 rw 00046fh i/o port p03 - extended port input level register epilr03 rw i/o map mb96(f)38x (15 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 48 2008-2-4 000470h i/o port p04 - extended port input level register epilr04 rw 000471h i/o port p05 - extended port input level register epilr05 rw 000472h i/o port p06 - extended port input level register epilr06 rw 000473h reserved - 000474h i/o port p08 - extended port input level register epilr08 rw 000475h i/o port p09 - extended port input level register epilr09 rw 000476h i/o port p10 - extended port input level register epilr10 rw 000477h i/o port p11 - extended port input level register epilr11 rw 000478h i/o port p12 - extended port input level register epilr12 rw 000479h i/o port p13 - extended port input level register epilr13 rw 00047ah- 00047fh reserved - 000480h i/o port p00 - port output drive register podr00 rw 000481h i/o port p01 - port output drive register podr01 rw 000482h i/o port p02 - port output drive register podr02 rw 000483h i/o port p03 - port output drive register podr03 rw 000484h i/o port p04 - port output drive register podr04 rw 000485h i/o port p05 - port output drive register podr05 rw 000486h i/o port p06 - port output drive register podr06 rw 000487h reserved - 000488h i/o port p08 - port output drive register podr08 rw 000489h i/o port p09 - port output drive register podr09 rw 00048ah i/o port p10 - port output drive register podr10 rw 00048bh i/o port p11 - port output drive register podr11 rw 00048ch i/o port p12 - port output drive register podr12 rw 00048dh i/o port p13 - port output drive register podr13 rw 00048eh- 00049bh reserved - 00049ch i/o port p08 - port high drive register phdr08 rw 00049dh i/o port p09 - port high drive register phdr09 rw 00049eh i/o port p10 - port high drive register phdr10 rw i/o map mb96(f)38x (16 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 49 00049fh- 0004a7h reserved - 0004a8h i/o port p00 - pull-up resistor control register pucr00 rw 0004a9h i/o port p01 - pull-up resistor control register pucr01 rw 0004aah i/o port p02 - pull-up resistor control register pucr02 rw 0004abh i/o port p03 - pull-up resistor control register pucr03 rw 0004ach i/o port p04 - pull-up resistor control register pucr04 rw 0004adh i/o port p05 - pull-up resistor control register pucr05 rw 0004aeh i/o port p06 - pull-up resistor control register pucr06 rw 0004afh reserved - 0004b0h i/o port p08 - pull-up resistor control register pucr08 rw 0004b1h i/o port p09 - pull-up resistor control register pucr09 rw 0004b2h i/o port p10 - pull-up resistor control register pucr10 rw 0004b3h i/o port p11 - pull-up resistor control register pucr11 rw 0004b4h i/o port p12 - pull-up resistor control register pucr12 rw 0004b5h i/o port p13 - pull-up resistor control register pucr13 rw 0004b6h- 0004bbh reserved - 0004bch i/o port p00 - external pin state register epsr00 r 0004bdh i/o port p01 - external pin state register epsr01 r 0004beh i/o port p02 - external pin state register epsr02 r 0004bfh i/o port p03 - external pin state register epsr03 r 0004c0h i/o port p04 - external pin state register epsr04 r 0004c1h i/o port p05 - external pin state register epsr05 r 0004c2h i/o port p06 - external pin state register epsr06 r 0004c3h reserved - 0004c4h i/o port p08 - external pin state register epsr08 r 0004c5h i/o port p09 - external pin state register epsr09 r 0004c6h i/o port p10 - external pin state register epsr10 r 0004c7h i/o port p11 - external pin state register epsr11 r 0004c8h i/o port p12 - external pin state register epsr12 r i/o map mb96(f)38x (17 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 50 2008-2-4 0004c9h i/o port p13 - external pin state register epsr13 r 0004cah- 0004cfh reserved - 0004d0h adc analog input enable register 0 ader0 rw 0004d1h adc analog input enable register 1 ader1 rw 0004d2h adc analog input enable register 2 ader2 rw 0004d3h adc analog input enable register 3 ader3 rw 0004d4h adc analog input enable register 4 ader4 rw 0004d5h reserved - 0004d6h peripheral resource relocation register 0 prrr0 rw 0004d7h peripheral resource relocation register 1 prrr1 rw 0004d8h peripheral resource relocation register 2 prrr2 rw 0004d9h peripheral resource relocation register 3 prrr3 rw 0004dah peripheral resource relocation register 4 prrr4 rw 0004dbh peripheral resource relocation register 5 prrr5 rw 0004dch peripheral resource relocation register 6 prrr6 rw 0004ddh peripheral resource relocation register 7 prrr7 rw 0004deh peripheral resource relocation register 8 prrr8 rw 0004dfh peripheral resource relocation register 9 prrr9 rw 0004e0h rtc - sub second register l wtbrl0 wtbr0 rw 0004e1h rtc - sub second register m wtbrh0 rw 0004e2h rtc - sub-second register h wtbr1 rw 0004e3h rtc - second register wtsr rw 0004e4h rtc - minutes wtmr rw 0004e5h rtc - hour wthr rw 0004e6h rtc - timer control extended register wtcer rw 0004e7h rtc - clock select register wtcksr rw 0004e8h rtc - timer control register low wtcrl wtcr rw 0004e9h rtc - timer control register high wtcrh rw 0004eah cal - calibration unit control register cucr rw i/o map mb96(f)38x (18 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 51 0004ebh reserved - 0004ech cal - duration timer data register low cutdl cutd rw 0004edh cal - duration timer data register high cutdh rw 0004eeh cal - calibration timer register 2 low cutr2l cutr2 r 0004efh cal - calibration timer register 2 high cutr2h r 0004f0h cal - calibration timer register 1 low cutr1l cutr1 r 0004f1h cal - calibration timer register 1 high cutr1h r 0004f2h- 0004f9h reserved - 0004fah rlt - timer input select (for cascading) tmisr rw 0004fbh- 00051fh reserved - 000520h usart4 - serial mode register smr4 rw 000521h usart4 - serial control register scr4 rw 000522h usart4 - tx register tdr4 w 000522h usart4 - rx register rdr4 r 000523h usart4 - serial status ssr4 rw 000524h usart4 - control/com. register (internal) eccr4 rw 000525h usart4 - ext. status register escr4 rw 000526h usart4 - baud rate generator register low bgrl4 bgr4 rw 000527h usart4 - baud rate generator register high bgrh4 rw 000528h usart4 - extended serial interrupt register esir4 rw 000529h reserved - 00052ah usart5 - serial mode register smr5 rw 00052bh usart5 - serial control register scr5 rw 00052ch usart5 - rx register tdr5 w 00052ch usart5 - tx register rdr5 r 00052dh usart5 - serial status ssr5 rw 00052eh usart5 - control/com. register eccr5 rw 00052fh usart5 - ext. status register escr5 rw 000530h usart5 - baud rate generator register low bgrl5 bgr5 rw i/o map mb96(f)38x (19 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 52 2008-2-4 000531h usart5 - baud rate generator register high bgrh5 rw 000532h usart5 - extended serial interrupt register esir5 rw 000533h- 00055fh reserved - 000560h alarm0 - control status register acsr0 rw 000561h alarm0 - extended control status register aecsr0 rw 000562h alarm1 - control status register acsr1 rw 000563h alarm1 - extended control status register aecsr1 rw 000564h ppg6 - timer register ptmr6 r 000565h ppg6 - timer register r 000566h ppg6 - period setting register pcsr6 w 000567h ppg6 - period setting register w 000568h ppg6 - duty cycle register pdut6 w 000569h ppg6 - duty cycle register w 00056ah ppg6 - control status register low pcnl6 pcn6 rw 00056bh ppg6 - control status register high pcnh6 rw 00056ch ppg7 - timer register ptmr7 r 00056dh ppg7 - timer register r 00056eh ppg7 - period setting register pcsr7 w 00056fh ppg7 - period setting register w 000570h ppg7 - duty cycle register pdut7 w 000571h ppg7 - duty cycle register w 000572h ppg7 - control status register low pcnl7 pcn7 rw 000573h ppg7 - control status register high pcnh7 rw 000574h- 0005dfh reserved - 0005e0h smc0 - pwm control register pwc0 rw 0005e1h smc0 - extended control register (output enable) pwec0 rw 0005e2h smc0 - pwm compare register pwm 1 pwc10 rw 0005e3h smc0 - pwm compare register pwm 1 rw 0005e4h smc0 - pwm compare register pwm 2 pwc20 rw i/o map mb96(f)38x (20 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 53 0005e5h smc0 - pwm compare register pwm 2 rw 0005e6h smc0 - pwm select register pws10 rw 0005e7h smc0 - pwm select register pws20 rw 0005e8h- 0005e9h reserved - 0005eah smc1 - pwm control register pwc1 rw 0005ebh smc1 - extended control register (output enable) pwec1 rw 0005ech smc1 - pwm compare register pwm 1 pwc11 rw 0005edh smc1 - pwm compare register pwm 1 rw 0005eeh smc1 - pwm compare register pwm 2 pwc21 rw 0005efh smc1 - pwm compare register pwm 2 rw 0005f0h smc1 - pwm select register pws11 rw 0005f1h smc1 - pwm select register pws21 rw 0005f2h- 0005f3h reserved - 0005f4h smc2 - pwm control register pwc2 rw 0005f5h smc2 - extended control register (output enable) pwec2 rw 0005f6h smc2 - pwm compare register pwm 1 pwc12 rw 0005f7h smc2 - pwm compare register pwm 1 rw 0005f8h smc2 - pwm compare register pwm 2 pwc22 rw 0005f9h smc2 - pwm compare register pwm 2 rw 0005fah smc2 - pwm select register pws12 rw 0005fbh smc2 - pwm select register pws22 rw 0005fch- 0005fdh reserved - 0005feh smc3 - pwm control register pwc3 rw 0005ffh smc3 - extended control register (output enable) pwec3 rw 000600h smc3 - pwm compare register pwm 1 pwc13 rw 000601h smc3 - pwm compare register pwm 1 rw 000602h smc3 - pwm compare register pwm 2 pwc23 rw 000603h smc3 - pwm compare register pwm 2 rw i/o map mb96(f)38x (21 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 54 2008-2-4 000604h smc3 - pwm select register pws13 rw 000605h smc3 - pwm select register pws23 rw 000606h- 000607h reserved - 000608h smc4 - pwm control register pwc4 rw 000609h smc4 - extended control register (output enable) pwec4 rw 00060ah smc4 - pwm compare register pwm 1 pwc14 rw 00060bh smc4 - pwm compare register pwm 1 rw 00060ch smc4 - pwm compare register pwm 2 pwc24 rw 00060dh smc4 - pwm compare register pwm 2 rw 00060eh smc4 - pwm select register pws14 rw 00060fh smc4 - pwm select register pws24 rw 000610h- 00061bh reserved - 00061ch lcd - output enable register 0 (seg 7-0) lcder0 rw 00061dh lcd - output enable register 1 (seg 15-8) lcder1 rw 00061eh lcd - output enable register 2 (seg 23-16) lcder2 rw 00061fh lcd - output enable register 3 (seg 31-24) lcder3 rw 000620h lcd - output enable register 4 (seg 39-32) lcder4 rw 000621h lcd - output enable register 5 (seg 47-40) lcder5 rw 000622h lcd - output enable register 6 (seg 55-48) lcder6 rw 000623h lcd - output enable register 7 (seg 63-56) lcder7 rw 000624h lcd - output enable register 8 (seg 71-64) lcder8 rw 000625h reserved - 000626h lcd - output enable register v (vx) lcdver rw 000627h lcd - extended control register lecr rw 000628h lcd - common pin switching register lcdcmr rw 000629h lcd - control register lcr rw 00062ah lcd - data register for segment 1-0 vram0 rw 00062bh lcd - data register for segment 3-2 vram1 rw 00062ch lcd - data register for segment 5-4 vram2 rw i/o map mb96(f)38x (22 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 55 00062dh lcd - data register for segment 7-6 vram3 rw 00062eh lcd - data register for segment 9-8 vram4 rw 00062fh lcd - data register for segment 11-10 vram5 rw 000630h lcd - data register for segment 13-12 vram6 rw 000631h lcd - data register for segment 15-14 vram7 rw 000632h lcd - data register for segment 17-16 vram8 rw 000633h lcd - data register for segment 19-18 vram9 rw 000634h lcd - data register for segment 21-20 vram10 rw 000635h lcd - data register for segment 23-22 vram11 rw 000636h lcd - data register for segment 25-24 vram12 rw 000637h lcd - data register for segment 27-26 vram13 rw 000638h lcd - data register for segment 29-28 vram14 rw 000639h lcd - data register for segment 31-30 vram15 rw 00063ah lcd - data register for segment 33-32 vram16 rw 00063bh lcd - data register for segment 35-34 vram17 rw 00063ch lcd - data register for segment 37-36 vram18 rw 00063dh lcd - data register for segment 39-38 vram19 rw 00063eh lcd - data register for segment 41-40 vram20 rw 00063fh lcd - data register for segment 43-42 vram21 rw 000640h lcd - data register for segment 45-44 vram22 rw 000641h lcd - data register for segment 47-46 vram23 rw 000642h lcd - data register for segment 49-48 vram24 rw 000643h lcd - data register for segment 51-50 vram25 rw 000644h lcd - data register for segment 53-52 vram26 rw 000645h lcd - data register for segment 55-54 vram27 rw 000646h lcd - data register for segment 57-56 vram28 rw 000647h lcd - data register for segment 59-58 vram29 rw 000648h lcd - data register for segment 61-60 vram30 rw 000649h lcd - data register for segment 63-62 vram31 rw 00064ah lcd - data register for segment 65-64 vram32 rw i/o map mb96(f)38x (23 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 56 2008-2-4 00064bh- 00065fh reserved - 000660h peripheral resource relocation register 10 prrr10 rw 000661h peripheral resource relocation register 11 prrr11 rw 000662h peripheral resource relocation register 12 prrr12 rw 000663h peripheral resource relocation register 13 prrr13 w 000664h- 0006dfh reserved - 0006e0h external bus - area con?uration register 0 low eacl0 eac0 rw 0006e1h external bus - area con?uration register 0 high each0 rw 0006e2h external bus - area con?uration register 1 low eacl1 eac1 rw 0006e3h external bus - area con?uration register 1 high each1 rw 0006e4h external bus - area con?uration register 2 low eacl2 eac2 rw 0006e5h external bus - area con?uration register 2 high each2 rw 0006e6h external bus - area con?uration register 3 low eacl3 eac3 rw 0006e7h external bus - area con?uration register 3 high each3 rw 0006e8h external bus - area con?uration register 4 low eacl4 eac4 rw 0006e9h external bus - area con?uration register 4 high each4 rw 0006eah external bus - area con?uration register 5 low eacl5 eac5 rw 0006ebh external bus - area con?uration register 5 high each5 rw 0006ech external bus - area select register 2 eas2 rw 0006edh external bus - area select register 3 eas3 rw 0006eeh external bus - area select register 4 eas4 rw 0006efh external bus - area select register 5 eas5 rw 0006f0h external bus - mode register ebm rw 0006f1h external bus - clock and function register ebcf rw 0006f2h external bus - address output enable register 0 ebae0 rw 0006f3h external bus - address output enable register 1 ebae1 rw 0006f4h external bus - address output enable register 2 ebae2 rw 0006f5h external bus - control signal register ebcs rw i/o map mb96(f)38x (24 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 57 0006f6h- 0006ffh reserved - 000700h can0 - control register low ctrlrl0 ctrlr0 rw 000701h can0 - control register high (reserved) ctrlrh0 r 000702h can0 - status register low statrl0 statr0 rw 000703h can0 - status register high (reserved) statrh0 r 000704h can0 - error counter low (transmit) errcntl0 errcnt0 r 000705h can0 - error counter high (receive) errcnth0 r 000706h can0 - bit timing register low btrl0 btr0 rw 000707h can0 - bit timing register high btrh0 rw 000708h can0 - interrupt register low intrl0 intr0 r 000709h can0 - interrupt register high intrh0 r 00070ah can0 - test register low testrl0 testr0 rw 00070bh can0 - test register high (reserved) testrh0 r 00070ch can0 - brp extension register low brperl0 brper0 rw 00070dh can0 - brp extension register high (reserved) brperh0 r 00070eh- 00070fh reserved - 000710h can0 - if1 command request register low if1creql0 if1creq0 rw 000711h can0 - if1 command request register high if1creqh0 rw 000712h can0 - if1 command mask register low if1cmskl0 if1cmsk0 rw 000713h can0 - if1 command mask register high (reserved) if1cmskh0 r 000714h can0 - if1 mask 1 register low if1msk1l0 if1msk10 rw 000715h can0 - if1 mask 1 register high if1msk1h0 rw 000716h can0 - if1 mask 2 register low if1msk2l0 if1msk20 rw 000717h can0 - if1 mask 2 register high if1msk2h0 rw 000718h can0 - if1 arbitration 1 register low if1arb1l0 if1arb10 rw 000719h can0 - if1 arbitration 1 register high if1arb1h0 rw 00071ah can0 - if1 arbitration 2 register low if1arb2l0 if1arb20 rw 00071bh can0 - if1 arbitration 2 register high if1arb2h0 rw i/o map mb96(f)38x (25 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 58 2008-2-4 00071ch can0 - if1 message control register low if1mctrl0 if1mctr0 rw 00071dh can0 - if1 message control register high if1mctrh0 rw 00071eh can0 - if1 data a1 low if1dta1l0 if1dta10 rw 00071fh can0 - if1 data a1 high if1dta1h0 rw 000720h can0 - if1 data a2 low if1dta2l0 if1dta20 rw 000721h can0 - if1 data a2 high if1dta2h0 rw 000722h can0 - if1 data b1 low if1dtb1l0 if1dtb10 rw 000723h can0 - if1 data b1 high if1dtb1h0 rw 000724h can0 - if1 data b2 low if1dtb2l0 if1dtb20 rw 000725h can0 - if1 data b2 high if1dtb2h0 rw 000726h- 00073fh reserved - 000740h can0 - if2 command request register low if2creql0 if2creq0 rw 000741h can0 - if2 command request register high if2creqh0 rw 000742h can0 - if2 command mask register low if2cmskl0 if2cmsk0 rw 000743h can0 - if2 command mask register high (reserved) if2cmskh0 r 000744h can0 - if2 mask 1 register low if2msk1l0 if2msk10 rw 000745h can0 - if2 mask 1 register high if2msk1h0 rw 000746h can0 - if2 mask 2 register low if2msk2l0 if2msk20 rw 000747h can0 - if2 mask 2 register high if2msk2h0 rw 000748h can0 - if2 arbitration 1 register low if2arb1l0 if2arb10 rw 000749h can0 - if2 arbitration 1 register high if2arb1h0 rw 00074ah can0 - if2 arbitration 2 register low if2arb2l0 if2arb20 rw 00074bh can0 - if2 arbitration 2 register high if2arb2h0 rw 00074ch can0 - if2 message control register low if2mctrl0 if2mctr0 rw 00074dh can0 - if2 message control register high if2mctrh0 rw 00074eh can0 - if2 data a1 low if2dta1l0 if2dta10 rw 00074fh can0 - if2 data a1 high if2dta1h0 rw 000750h can0 - if2 data a2 low if2dta2l0 if2dta20 rw 000751h can0 - if2 data a2 high if2dta2h0 rw i/o map mb96(f)38x (26 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 59 000752h can0 - if2 data b1 low if2dtb1l0 if2dtb10 rw 000753h can0 - if2 data b1 high if2dtb1h0 rw 000754h can0 - if2 data b2 low if2dtb2l0 if2dtb20 rw 000755h can0 - if2 data b2 high if2dtb2h0 rw 000756h- 00077fh reserved - 000780h can0 - transmission request 1 register low treqr1l0 treqr10 r 000781h can0 - transmission request 1 register high treqr1h0 r 000782h can0 - transmission request 2 register low treqr2l0 treqr20 r 000783h can0 - transmission request 2 register high treqr2h0 r 000784h- 00078fh reserved - 000790h can0 - new data 1 register low newdt1l0 newdt10 r 000791h can0 - new data 1 register high newdt1h0 r 000792h can0 - new data 2 register low newdt2l0 newdt20 r 000793h can0 - new data 2 register high newdt2h0 r 000794h- 00079fh reserved - 0007a0h can0 - interrupt pending 1 register low intpnd1l0 intpnd10 r 0007a1h can0 - interrupt pending 1 register high intpnd1h0 r 0007a2h can0 - interrupt pending 2 register low intpnd2l0 intpnd20 r 0007a3h can0 - interrupt pending 2 register high intpnd2h0 r 0007a4h- 0007afh reserved - 0007b0h can0 - message valid 1 register low msgval1l0 msgval10 r 0007b1h can0 - message valid 1 register high msgval1h0 r 0007b2h can0 - message valid 2 register low msgval2l0 msgval20 r 0007b3h can0 - message valid 2 register high msgval2h0 r 0007b4h- 0007cdh reserved - 0007ceh can0 - output enable register coer0 rw 0007cfh reserved - i/o map mb96(f)38x (27 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 60 2008-2-4 0007d0h sg0 - sound generator control register low sgcrl0 sgcr0 rw 0007d1h sg0 - sound generator control register high sgcrh0 rw 0007d2h sg0 - sound generator frequency register sgfr0 rw 0007d3h sg0 - sound generator amplitude register sgar0 rw 0007d4h sg0 - sound generator decrement register sgdr0 rw 0007d5h sg0 - sound generator tone register sgtr0 rw 0007d6h sg1 - sound generator control register low sgcrl1 sgcr1 rw 0007d7h sg1 - sound generator control register high sgcrh1 rw 0007d8h sg1 - sound generator frequency register sgfr1 rw 0007d9h sg1 - sound generator amplitude register sgar1 rw 0007dah sg1 - sound generator decrement register sgdr1 rw 0007dbh sg1 - sound generator tone register sgtr1 rw 0007dch- 0007ffh reserved - 000800h can1 - control register low ctrlrl1 ctrlr1 rw 000801h can1 - control register high (reserved) ctrlrh1 r 000802h can1 - status register low statrl1 statr1 rw 000803h can1 - status register high (reserved) statrh1 r 000804h can1 - error counter low (transmit) errcntl1 errcnt1 r 000805h can1 - error counter high (receive) errcnth1 r 000806h can1 - bit timing register low btrl1 btr1 rw 000807h can1 - bit timing register high btrh1 rw 000808h can1 - interrupt register low intrl1 intr1 r 000809h can1 - interrupt register high intrh1 r 00080ah can1 - test register low testrl1 testr1 rw 00080bh can1 - test register high (reserved) testrh1 r 00080ch can1 - brp extension register low brperl1 brper1 rw 00080dh can1 - brp extension register high (reserved) brperh1 r 00080eh- 00080fh reserved - 000810h can1 - if1 command request register low if1creql1 if1creq1 rw i/o map mb96(f)38x (28 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 61 000811h can1 - if1 command request register high if1creqh1 rw 000812h can1 - if1 command mask register low if1cmskl1 if1cmsk1 rw 000813h can1 - if1 command mask register high (reserved) if1cmskh1 r 000814h can1 - if1 mask 1 register low if1msk1l1 if1msk11 rw 000815h can1 - if1 mask 1 register high if1msk1h1 rw 000816h can1 - if1 mask 2 register low if1msk2l1 if1msk21 rw 000817h can1 - if1 mask 2 register high if1msk2h1 rw 000818h can1 - if1 arbitration 1 register low if1arb1l1 if1arb11 rw 000819h can1 - if1 arbitration 1 register high if1arb1h1 rw 00081ah can1 - if1 arbitration 2 register low if1arb2l1 if1arb21 rw 00081bh can1 - if1 arbitration 2 register high if1arb2h1 rw 00081ch can1 - if1 message control register low if1mctrl1 if1mctr1 rw 00081dh can1 - if1 message control register high if1mctrh1 rw 00081eh can1 - if1 data a1 low if1dta1l1 if1dta11 rw 00081fh can1 - if1 data a1 high if1dta1h1 rw 000820h can1 - if1 data a2 low if1dta2l1 if1dta21 rw 000821h can1 - if1 data a2 high if1dta2h1 rw 000822h can1 - if1 data b1 low if1dtb1l1 if1dtb11 rw 000823h can1 - if1 data b1 high if1dtb1h1 rw 000824h can1 - if1 data b2 low if1dtb2l1 if1dtb21 rw 000825h can1 - if1 data b2 high if1dtb2h1 rw 000826h- 00083fh reserved - 000840h can1 - if2 command request register low if2creql1 if2creq1 rw 000841h can1 - if2 command request register high if2creqh1 rw 000842h can1 - if2 command mask register low if2cmskl1 if2cmsk1 rw 000843h can1 - if2 command mask register high (reserved) if2cmskh1 r 000844h can1 - if2 mask 1 register low if2msk1l1 if2msk11 rw 000845h can1 - if2 mask 1 register high if2msk1h1 rw i/o map mb96(f)38x (29 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 62 2008-2-4 000846h can1 - if2 mask 2 register low if2msk2l1 if2msk21 rw 000847h can1 - if2 mask 2 register high if2msk2h1 rw 000848h can1 - if2 arbitration 1 register low if2arb1l1 if2arb11 rw 000849h can1 - if2 arbitration 1 register high if2arb1h1 rw 00084ah can1 - if2 arbitration 2 register low if2arb2l1 if2arb21 rw 00084bh can1 - if2 arbitration 2 register high if2arb2h1 rw 00084ch can1 - if2 message control register low if2mctrl1 if2mctr1 rw 00084dh can1 - if2 message control register high if2mctrh1 rw 00084eh can1 - if2 data a1 low if2dta1l1 if2dta11 rw 00084fh can1 - if2 data a1 high if2dta1h1 rw 000850h can1 - if2 data a2 low if2dta2l1 if2dta21 rw 000851h can1 - if2 data a2 high if2dta2h1 rw 000852h can1 - if2 data b1 low if2dtb1l1 if2dtb11 rw 000853h can1 - if2 data b1 high if2dtb1h1 rw 000854h can1 - if2 data b2 low if2dtb2l1 if2dtb21 rw 000855h can1 - if2 data b2 high if2dtb2h1 rw 000856h- 00087fh reserved - 000880h can1 - transmission request 1 register low treqr1l1 treqr11 r 000881h can1 - transmission request 1 register high treqr1h1 r 000882h can1 - transmission request 2 register low treqr2l1 treqr21 r 000883h can1 - transmission request 2 register high treqr2h1 r 000884h- 00088fh reserved - 000890h can1 - new data 1 register low newdt1l1 newdt11 r 000891h can1 - new data 1 register high newdt1h1 r 000892h can1 - new data 2 register low newdt2l1 newdt21 r 000893h can1 - new data 2 register high newdt2h1 r 000894h- 00089fh reserved - 0008a0h can1 - interrupt pending 1 register low intpnd1l1 intpnd11 r i/o map mb96(f)38x (30 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 63 0008a1h can1 - interrupt pending 1 register high intpnd1h1 r 0008a2h can1 - interrupt pending 2 register low intpnd2l1 intpnd21 r 0008a3h can1 - interrupt pending 2 register high intpnd2h1 r 0008a4h- 0008afh reserved - 0008b0h can1 - message valid 1 register low msgval1l1 msgval11 r 0008b1h can1 - message valid 1 register high msgval1h1 r 0008b2h can1 - message valid 2 register low msgval2l1 msgval21 r 0008b3h can1 - message valid 2 register high msgval2h1 r 0008b4h- 0008cdh reserved - 0008ceh can1 - output enable register coer1 rw 0008cfh- 000bffh reserved - i/o map mb96(f)38x (31 / 31) address register abbreviation 8-bit access abbreviation 16-bit access access
preliminary mb96380 series fme-mb96380 rev 8 64 2008-2-4 interrupt vector table interrupt vector table mb96(f)38x (1 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description 0 3fc callv0 no - 1 3f8 callv1 no - 2 3f4 callv2 no - 3 3f0 callv3 no - 4 3ec callv4 no - 5 3e8 callv5 no - 6 3e4 callv6 no - 7 3e0 callv7 no - 8 3dc reset no - 9 3d8 int9 no - 10 3d4 exception no - 11 3d0 nmi no - non-maskable interrupt 12 3cc dly no 12 delayed interrupt 13 3c8 rc_timer no 13 rc timer 14 3c4 mc_timer no 14 main clock timer 15 3c0 sc_timer no 15 sub clock timer 16 3bc reserved no 16 reserved 17 3b8 extint0 yes 17 external interrupt 0 18 3b4 extint1 yes 18 external interrupt 1 19 3b0 extint2 yes 19 external interrupt 2 20 3ac extint3 yes 20 external interrupt 3 21 3a8 extint4 yes 21 external interrupt 4 22 3a4 extint5 yes 22 external interrupt 5 23 3a0 extint6 yes 23 external interrupt 6 24 39c extint7 yes 24 external interrupt 7 25 398 can0 no 25 can controller 0 26 394 can1* no 26 can controller 1 27 390 ppg0 yes 27 programmable pulse generator 0 28 38c ppg1 yes 28 programmable pulse generator 1 29 388 ppg2 yes 29 programmable pulse generator 2 30 384 ppg3 yes 30 programmable pulse generator 3 31 380 ppg4 yes 31 programmable pulse generator 4 32 37c ppg5 yes 32 programmable pulse generator 5
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 65 33 378 ppg6 yes 33 programmable pulse generator 6 34 374 ppg7 yes 34 programmable pulse generator 7 35 370 rlt0 yes 35 reload timer 0 36 36c rlt1 yes 36 reload timer 1 37 368 rlt2 yes 37 reload timer 2 38 364 rlt3 yes 38 reload timer 3 39 360 ppgrlt yes 39 reload timer 6 - dedicated for ppg 40 35c icu0 yes 40 input capture unit 0 41 358 icu1 yes 41 input capture unit 1 42 354 icu2 yes 42 input capture unit 2 43 350 icu3 yes 43 input capture unit 3 44 34c icu4 yes 44 input capture unit 4 45 348 icu5 yes 45 input capture unit 5 46 344 icu6 yes 46 input capture unit 6 47 340 icu7 yes 47 input capture unit 7 48 33c ocu0 yes 48 output compare unit 0 49 338 ocu1 yes 49 output compare unit 1 50 334 ocu2 yes 50 output compare unit 2 51 330 ocu3 yes 51 output compare unit 3 52 32c frt0 yes 52 free running timer 0 53 328 frt1 yes 53 free running timer 1 54 324 rtc0 no 54 real timer clock 55 320 cal0 no 55 clock calibration unit 56 31c sg0 no 56 sound generator 0 57 318 sg1 no 57 sound generator 1 58 314 iic0 yes 58 i2c interface 59 310 adc0 yes 59 a/d converter 60 30c alarm0 no 60 alarm comparator 0 61 308 alarm1* no 61 alarm comparator 1 62 304 linr0 yes 62 lin usart 0 rx 63 300 lint0 yes 63 lin usart 0 tx 64 2fc linr1 yes 64 lin usart 1 rx 65 2f8 lint1 yes 65 lin usart 1 tx 66 2f4 linr2 yes 66 lin usart 2 rx 67 2f0 lint2 yes 67 lin usart 2 tx interrupt vector table mb96(f)38x (2 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description
preliminary mb96380 series fme-mb96380 rev 8 66 2008-2-4 68 2ec linr4 yes 68 lin usart 4 rx 69 2e8 lint4 yes 69 lin usart 4 tx 70 2e4 linr5 yes 70 lin usart 5 rx 71 2e0 lint5 yes 71 lin usart 5 tx 72 2dc flash_a no 72 flash memory a (only flash devices) 73 2d8 flash_b no 73 flash memory b (only mb96f388/f389) *: alarm1 and can1 are not included on mb96384 and mb96(f)385 devices interrupt vector table mb96(f)38x (3 / 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 67 handling devices special care is required for the following when handling the device: latch-up prevention unused pins handling external clock usage unused sub clock signal notes on pll clock mode operation power supply pins (v cc /v ss ) crystal oscillator circuit turn on sequence of power supply to a/d converter and analog inputs pin handling when not using the a/d converter notes on energization stabilization of power supply voltage smc power supply pins 1. latch-up prevention cmos ic chips may suffer latch-up under the following conditions: a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc and v ss . the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dramatically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 2. unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. they must therefore be pulled up or pulled down through resistors. to prevent latch- up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. external clock usage the permitted frequency range of an external clock depends on the oscillator type and configuration. see ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 1. single phase external clock when using a single phase external clock, x0 pin must be driven and x1 pin left open. 2. opposite phase external clock x0 x1
preliminary mb96380 series fme-mb96380 rev 8 68 2008-2-4 when using an opposite phase external clock, x1 (x1a) must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. 4. unused sub clock signal if the pins x0a and x1a are not connected to an oscillator, a pull-down resistor must be connected on the x0a pin and the x1a pin must be left open. 5. notes on pll clock mode operation if the pll clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc / v ss ) it is required that all v cc -level as well as all v ss -level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. ? cc and v ss must be connected to the device from the power supply with lowest possible impedance. as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 f between v cc and v ss as close as possible to v cc and v ss pins. 7. crystal oscillator circuit noise at x0 or x1 pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu system at the quartz manufacturer. 8. turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, the voltage must not exceed avrh or av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. pin handling when not using the a/d converter it is required to connect the unused pins of the a/d converter as av cc = v cc , av ss = avrh = avrl = v ss . 10. notes on energization to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 s from 0.2 v to 2.7 v. x0 x1
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 69 11. stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety range of the vcc power supply voltage, a malfunction may occur. the vcc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 hz) fall within 10% of the standard vcc power supply voltage and the transient fluctuation rate becomes 0.1v/ s or less in instantaneous fluctuation for power supply switching. 12. smc power supply pins all dv ss pins must be set to the same level as the v ss pins. the dv cc power supply level can be set independently of the v cc power supply level. however note that the smc i/o pin state is undefined if dv cc is powered on and v cc is below 3v. to avoid this, we recommend to always power v cc before dv cc .
preliminary mb96380 series fme-mb96380 rev 8 70 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 71 electrical characteristics 1. absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 ad converter voltage references avrh, avrl v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss smc power supply dv cc v ss - 0.3 v ss + 6.0 v see *7 lcd power supply voltage v0 to v3 v ss - 0.3 v ss + 6.0 v v0 to v3 must not exceed v cc input voltage v i v ss - 0.3 v ss + 6.0 v v i (d)v cc + 0.3v *2 output voltage v o v ss - 0.3 v ss + 6.0 v v o (d)v cc + 0.3v *2 maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/ o pins *3 total maximum clamp current |i clamp | - 40 ma applicable to general purpose i/ o pins *3 ??level maximum output current i ol1 - 15 ma normal outputs with driving strength set to 5ma i olsmc - 40 ma high current outputs with driv- ing strength set to 30ma ??level average output current i olav1 - 5 ma normal outputs with driving strength set to 5ma i olavsmc - 30 ma high current outputs with driv- ing strength set to 30ma ??level maximum overall output current i ol1 - 100 ma normal outputs i olsmc - 330 ma high current outputs ??level average overall output current i olav1 - 50 ma normal outputs i olavsmc - 250 ma high current outputs ??level maximum output current i oh1 - -15 ma normal outputs with driving strength set to 5ma i ohsmc - -40 ma high current outputs with driv- ing strength set to 30ma ??level average output current i ohav1 - -5 ma normal outputs with driving strength set to 5ma i ohavsmc - -30 ma high current outputs with driv- ing strength set to 30ma
preliminary mb96380 series fme-mb96380 rev 8 72 2008-2-4 *1: av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. *2: v i and v o should not exceed (d)v cc + 0.3 v. v i should also not exceed the speci?d ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating super- sedes the v i rating. input/output voltages of high current ports depend on dv cc. input/output voltages of standard ports depend on v cc. *3: ? applicable to all general purpose i/o pins (pnn_m) except i/o pins with seg or com functionality. ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not ?ed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suf?ient to operate the power reset (except devices with persistent low voltage ? level maximum overall output current i oh1 - -100 ma normal outputs i ohsmc - -330 ma high current outputs ??level average overall output current i ohav1 - -50 ma normal outputs i ohasmc - -250 ma high current outputs permitted power dissipation (flash de- vices) *4 p d - 370 *5 mw t a =105 o c - 740 *5 mw t a =85 o c - 1000 *5 mw t a =70 o c - 460 *5 mw t a =125 o c, no flash program/ erase *6 - 800 *5 mw t a =105 o c, no flash program/ erase *6 permitted power dissipation (mask rom devices) *4 p d - 310 *5 mw t a =105 o c - 625 *5 mw t a =85 o c - 800 *5 mw t a =70 o c - 390 *5 mw t a =125 o c *6 - 700 *5 mw t a =105 o c *6 operating ambient temperature t a 0 +70 o c mb96v300b -40 +105 -40 +125 *6 storage temperature t stg -55 +150 o c parameter symbol rating unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 73 reset in internal vector mode). ? no +b signal must be applied to any lcd i/o pin (including unused seg/com pins). ? sample recommended circuits: *4: the maximum permitted power dissipation depends on the ambient temperature, the air ?w velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol * i ol + v oh * i oh ) (io load power dissipation, sum is performed on all io ports) p int = v cc * (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the ?c characteristics and depends on the selected operation mode and clock frequency and the usage of functions like flash programming or the clock modulator. i a is the analog current consumption into av cc . *5: worst case value for a package mounted on single layer pcb at speci?d t a without air ?w. *6: please contact fujitsu for reliability limitations when using under these conditions. *7: if dv cc is powered before v cc , then smc i/o pins state is unde?ed. to avoid this, we recommend to always power v cc before dv cc . it is not necessary to set v cc and dv cc to the same value. p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v)
preliminary mb96380 series fme-mb96380 rev 8 74 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 75 2. recommended conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are guaranteed when the device is operated within these ranges. semiconductor devices must always be operated within their recommended operating condition ranges. oper- ation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu repre- sentatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , dv cc 3.0 - 5.5 v smoothing capacitor at c pin c s 4.7 - 10 f use a low inductance capacitor (for example x7r ceramic ca- pacitor)
preliminary mb96380 series fme-mb96380 rev 8 76 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 77 3. dc characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min typ max input ??voltage v ih port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected 0.8 v cc - (d)v cc + 0.3 v cmos hysteresis 0.7/0.3 input se- lected 0.7 v cc - (d)v cc + 0.3 v (d)v cc 4.5v 0.74 v cc - (d)v cc + 0.3 v (d)v cc < 4.5v automotive hysteresis input selected 0.8 v cc - (d)v cc + 0.3 v ttl input select- ed 2.0 - (d)v cc + 0.3 v v ihx0f x0 external clock in ?ast clock input mode 0.8 v cc - v cc + 0.3 v not available in mb96f386xxa/ f387xxa v ihx0s x0,x1, x0a,x1a external clock in ?scillation mode 2.5 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v cmos hysteresis in- put v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v input ??voltage v il port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected v ss - 0.3 - 0.2 (d)v cc v cmos hysteresis 0.7/0.3 input se- lected v ss - 0.3 - 0.3 (d)v cc v automotive hysteresis input selected v ss - 0.3 - 0.5 (d)v cc v (d)v cc 4.5v v ss - 0.3 - 0.46 (d)v cc (d)v cc < 4.5v ttl input select- ed v ss - 0.3 - 0.8 v v ilx0f x0 external clock in ?ast clock input mode v ss - 0.3 - 0.2 v cc v not available in mb96f386xxa/ f387xxa v ilx0s x0,x1, x0a,x1a external clock in ?scillation mode v ss - 0.3 -0.5 v v ilr rstx - v ss - 0.3 - 0.2 v cc v cmos hysteresis in- put v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v
preliminary mb96380 series fme-mb96380 rev 8 78 2008-2-4 output ? voltage v oh2 normal and high current outputs 4.5v (d)v cc 5.5v i oh = -2ma (d)v cc - 0.5 -- v driving strength set to 2ma 3.0v (d)v cc < 4.5v i oh = -1.6ma v oh5 normal and high current outputs 4.5v (d)v cc 5.5v i oh = -5ma (d)v cc - 0.5 -- v driving strength set to 5ma 3.0v (d)v cc < 4.5v i oh = -3ma v oh30 high cur- rent out- puts 4.5v dv cc 5.5v i oh = -30ma dv cc - 0.5 -- v driving strength set to 30ma 3.0v dv cc < 4.5v i oh = -20ma v oh3 i 2 c outputs 4.5v v cc 5.5v i oh = -3ma v cc - 0.5 -- v 3.0v v cc < 4.5v i oh = -2ma output ??voltage v ol2 normal and high current outputs 4.5v (d)v cc 5.5v i ol = +2ma - - 0.4 v driving strength set to 2ma 3.0v (d)v cc < 4.5v i ol = +1.6ma v ol5 normal and high current outputs 4.5v (d)v cc 5.5v i ol = +5ma - - 0.4 v driving strength set to 5ma 3.0v (d)v cc < 4.5v i ol = +3ma v ol30 high cur- rent out- puts 4.5v dv cc 5.5v i ol = +30ma - - 0.5 v driving strength set to 30ma 3.0v dv cc < 4.5v i ol = +20ma v ol3 i 2 c outputs 4.5v v cc 5.5v i ol = +3ma - - 0.4 v 3.0v v cc < 4.5v i ol = +2ma input leak current i il pnn_m dv cc = v cc = 5.5v v ss < v i < v cc -1 - +1 a (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min typ max
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 79 total lcd leak- age current i ilcd all seg/ com pins v cc = 5.0v -10 0.5 10 a maximum leakage current of all lcd pins internal lcd di- vide resistance r lcd between v3 and v ss 25 35 50 k ? pull-up resistance r up pnn_m, rstx - 25 50 100 k ? note: input/output voltages of high current ports depend on dv cc, of other ports on v cc. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min typ max
preliminary mb96380 series fme-mb96380 rev 8 80 2008-2-4 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit power supply cur- rent in run modes* i ccpll pll run mode with clks1/2 = 48mhz, clkb = clkp1/2 = 24mhz 35 44 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 0 flash/rom wait states 36 47 125?c pll run mode with clks1/2 = clkb = clkp1= 56mhz, clkp2 = 28mhz 44 57 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 2 flash/rom wait states (not for mb96f385/ f388/f389) 45 60 125?c pll run mode with clks1/2 = 96mhz, clkb = clkp1= 48mhz, clkp2 = 24mhz 49 62 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 1 flash/rom wait state mb96384/385 50 65 125?c pll run mode with clks1/2 = 80mhz, clkb = clkp1 = 40mhz, clkp2 = 20mhz 42 55 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 1 flash/rom wait state mb96f385/f388/f389 43 58 125?c pll run mode with clks1/2 = 72mhz, clkb = clkp1 = 36mhz, clkp2 = 18mhz 38 50 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 1 flash/rom wait state mb96f386/f387 39 53 125?c i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz 4.5 5.5 ma 25?c clkpll, clksc and clkrc stopped 1 flash/rom wait state 5.1 8.5 125?c i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = 2mhz 2.9 4 ma 25?c clkmc, clkpll and clksc stopped 1 flash/rom wait state 3.5 6.5 125?c
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 81 power supply cur- rent in run modes* i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 0 0.4 0.6 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 1 flash/rom wait state 0.9 3.5 125?c rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 1 0.15 0.25 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode, no flash pro- gramming/erasing allowed. 1 flash/rom wait state 0.65 3.2 125?c i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz 0.1 0.2 ma 25?c clkmc, clkpll and clkrc stopped, no flash programming/ erasing allowed. 1 flash/rom wait state 0.6 3 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96380 series fme-mb96380 rev 8 82 2008-2-4 power supply cur- rent in sleep modes* i ccspll pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz 9 10.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 9.7 13 125?c pll sleep mode with clks1/2 = clkp1= 56mhz, clkp2 = 28mhz 14 15.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v (not for mb96f385/ f388/f389) 14.8 18 125?c pll sleep mode with clks1/2 = 96mhz, clkp1= 48mhz, clkp2 = 24mhz 14 15.5 ma 25?c clkrc and clksc stopped. core voltage at 1.9v mb96384/385 14.8 18 125?c pll sleep mode with clks1/2 = 80mhz, clkp1 = 40mhz, clkp2 = 20mhz 11.7 13.2 ma 25?c clkrc and clksc stopped. core voltage at 1.9v mb96f385/f388/f389 12.5 15.7 125?c pll sleep mode with clks1/2 = 72mhz, clkp1 = 36mhz, clkp2 = 18mhz 10.5 12 ma 25?c clkrc and clksc stopped. core voltage at 1.9v mb96f386/f387 11.3 14.5 125?c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz 1.5 1.8 ma 25?c clkpll, clksc and clkrc stopped 2 4.5 125?c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = 2mhz 0.8 1.3 ma 25?c clkmc, clkpll and clksc stopped 1.4 4 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 83 power supply cur- rent in sleep modes* i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 0 0.3 0.5 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.8 3.4 125?c rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 1 0.06 0.15 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.56 3 125?c i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz 0.04 0.12 ma 25?c clkmc, clkpll and clkrc stopped 0.54 2.9 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96380 series fme-mb96380 rev 8 84 2008-2-4 power supply cur- rent in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clk- pll = 48mhz 1.6 2 ma 25?c clkrc and clksc stopped. core voltage at 1.9v 2.1 4.8 125?c i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 0.35 0.5 ma 25?c clkpll, clkrc and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125?c main timer mode with clkmc = 4mhz, smcr:lpmss = 1 0.1 0.15 ma 25?c clkpll, clkrc and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125?c i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 0.35 0.5 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.85 3.3 125?c rc timer mode with clkrc = 2mhz, smcr:lpmss = 1 0.1 0.15 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.6 2.9 125?c i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 0.3 0.45 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in high power mode 0.8 3.2 125?c rc timer mode with clkrc = 100khz, smcr:lpmss = 1 0.05 0.1 ma 25?c clkmc, clkpll and clksc stopped. volt- age regulator in low pow- er mode 0.55 2.8 125?c (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 85 power supply cur- rent in timer modes* i cctsub sub timer mode with clksc = 32khz 0.03 0.1 ma 25?c clkmc, clkpll and clkrc stopped 0.53 2.8 125?c stop mode i cch vrcr:lpmb[2:0] = ?10 0.02 0.08 ma 25?c core voltage at 1.8v 0.52 2.8 125?c vrcr:lpmb[2:0] = ?00 0.015 0.06 ma 25?c core voltage at 1.2v 0.4 2.3 125?c power supply cur- rent for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde=?? 90 140 a 25?c this current must be added to all power sup- ply currents above 100 150 125?c clock modulator current i ccclomo clock modulator en- abled (cmcr:pdx = ?? 3 4.5 ma - must be added to all cur- rent above flash write/erase current i ccflash current for one flash module 15 40 ma - must be added to all cur- rent above input capacitance c in - 15 30 pf high current outputs input capacitance c in - 5 15 pf other than c, av cc , av ss , avrh, avrl, v cc , v ss , dv cc , dv ss , high current outputs * the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter ?tandby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol condition value temp remarks typ max unit
preliminary mb96380 series fme-mb96380 rev 8 86 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 87 4. ac characteristics source clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using an oscillation circuit, pll off 0 - 16 mhz when using an opposite phase external clock, pll off 3.5 - 16 mhz when using an oscillation circuit or op- posite phase external clock, pll on clock frequency f fci x0 0 - 56 mhz when using a single phase external clock in ?ast clock input mode?(not available in mb96f386xxa and mb96f387xxa), pll off 3.5 - 56 mhz when using a single phase external clock in ?ast clock input mode?(not available in mb96f386xxa and mb96f387xxa), pll on clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an opposite phase external clock x0a 0 - 50 khz when using a single phase external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscil- lator 1 2 4 mhz when using fast frequency of rc oscil- lator clock frequency f clkvco - 50 - 200 mhz permitted vco output frequency of pll (clkvco) input clock pulse width p wh , p wl x0,x1 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a,x1a 5 - - s
preliminary mb96380 series fme-mb96380 rev 8 88 2008-2-4 x0 t cyl p wh p wl v il v ih x0a t cyll p whl p wll v il v ih
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 89 internal clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock fre- quency (clks1 and clks2) f clks1 , f clks2 0 92 0 96 mhz others than below 0 72 0 80 mhz mb96f385/f388/f389 0 68 0 74 mhz mb96f386/f387 internal cpu clock fre- quency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 0 52 0 56 mhz others than below 0 36 0 40 mhz mb96f385/f388/f389 internal peripheral clock frequency (clkp2) f clkp2 0 28 0 32 mhz others than below 0 26 0 28 mhz mb96f386/f387
preliminary mb96380 series fme-mb96380 rev 8 90 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 91 external reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc
preliminary mb96380 series fme-mb96380 rev 8 92 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 93 power on reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms 0.2 v t r 2.7v t off 0.2 v 0.2 v if the power supply is changed too rapidly, a power-on reset may occur. we recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the ?ure below. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed
preliminary mb96380 series fme-mb96380 rev 8 94 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 95 external input timing note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit used pin input func- tion min max input pulse width t inh t inl intn ? 200 ? ns external interrupt nmi nmi pnn_m 2*t clkp1 + 200 (t clkp1 =1/ f clkp1 ) ? ns general purpose io tinn reload timer ttgn ppg trigger input adtg ad converter trigger frckn free running timer external clock inn input capture v il v ih t inh v il v ih t inl external pin input
preliminary mb96380 series fme-mb96380 rev 8 96 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 97 slew rate high current outputs note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, dv cc = 3.0v to 5.5v, v ss = av ss = dv ss = 0v) parameter symbol pin condition value unit remarks min max output rise/fall time t r30 t f30 i/o circuit type m output driving strength set to ?0ma 15 ? ns v l v h v l v h t r30 t f30 slew rate output timing v h =v ol30 + 0.9 (v oh30 -v ol30 ) v l =v ol30 + 0.1 (v oh30 -v ol30 )
preliminary mb96380 series fme-mb96380 rev 8 98 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 99 external bus timing warning: the values given below are for an i/o driving strength io drive =5ma.ifio drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. basic timing ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 25 ? ns t chcl t cyc /2-5 t cyc /2+5 t clch t cyc /2-5 t cyc /2+5 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -20 20 ns t chcbl -20 20 t clcbh -20 20 t clcbl -20 20 eclk ale time t chlh ale, eclk ? -10 10 ns t chll -10 10 t cllh -10 10 t clll -10 10 eclk address valid time (non-multiplexed) t chav a[23:0], eclk ebm:nms=1 -15 15 ns t clav -15 15 eclk address valid time (multiplexed) t chav a[23:16], eclk ebm:nms=0 -15 15 ns t clav -15 15 t cladv ad[15:0], eclk ebm:nms=0 -15 15 ns t chadv -15 15 eclk rdx /wrx time t chrwh rdx, wrx, wrlx,wrhx, eclk ? -10 10 ns t chrwl -10 10 t clrwh -10 10 t clrwl -10 10 ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 30 ? ns t chcl t cyc /2-8 t cyc /2+8 t clch t cyc /2-8 t cyc /2+8
preliminary mb96380 series fme-mb96380 rev 8 100 2008-2-4 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -25 25 ns t chcbl -25 25 t clcbh -25 25 t clcbl -25 25 eclk ale time t chlh ale, eclk ? -15 15 ns t chll -15 15 t cllh -15 15 t clll -15 15 eclk address valid time (non-multiplexed) t chav a[23:0], eclk ebm:nms=1 -20 20 ns t clav -20 20 eclk address valid time (multiplexed) t chav a[23:16], eclk ebm:nms=0 -20 20 ns t clav -20 20 t cladv ad[15:0], eclk ebm:nms=0 -20 20 ns t chadv -20 20 eclk rdx /wrx time t chrwh rdx, wrx, wrlx, wrhx, eclk ? -15 15 ns t chrwl -15 15 t clrwh -15 15 t clrwl -15 15 ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter symbol pin condition value unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 101 refer to the hardware manual for detailed timing charts. eclk t cyc csn ale a[23:0] 0.2*vcc t chcl t chav t chcbl t chcbh lbx ubx t cllh t chll t chlh t clll t cladv ad[15:0] address t clav t chadv t clcbh t clcbl t chrwh t clrwh t clrwl t chrwl rdx wrx (wrlx, wrhx) 0.8*vcc t clch
preliminary mb96380 series fme-mb96380 rev 8 102 2008-2-4 bus timing (read) (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width (multiplexed) t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 5 ? ns ebm:nms=0 eacl:sts=1 t cyc ? 5 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 5 ? valid address ? ale time (multiplexed) t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 15 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 15 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 15 ? t advll ale,ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 15 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 15 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 15 ? ale ? address valid time (multiplexed) t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 -15 ? valid address ? rdx time (non-multiplexed) t avrl rdx, a[23:0] ebm:nms= 1 t cyc /2 ? 15 ? ns valid address ? rdx time (multiplexed) t avrl rdx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 15 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 15 ? t advrl rdx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 15 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 15 ? valid address ? valid data input (non-multiplexed) t avdv a[23:0], ad[15:0] ebm:nms= 1 ? 2t cyc ? 55 ns w/o cycle extension
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 103 valid address ? valid data input (multiplexed) t avdv a[23:16], ad[15:0] eacl:ace=0 ebm:nms=0 ? 3t cyc ? 55 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ? 4t cyc ? 55 t advdv ad[15:0] eacl:ace=0 ebm:nms=0 ? 5t cyc /2 ? 55 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ? 7t cyc /2 ? 55 rdx pulse width t rlrh rdx ? 3 t cyc /2 ? 5 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 50 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:0], ad[15:0] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 10 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 10 ? valid address ? eclk time t avch a[23:0], eclk ? t cyc ? 15 ? ns t advch ad[15:0], eclk t cyc /2 ? 15 ? rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 10 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 10 ? ns eacl:sts=1 ? 10 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 50 ns (t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 104 2008-2-4 (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width (multiplexed) t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 8 ? ns ebm:nms=0 eacl:sts=1 t cyc ? 8 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 8 ? valid address ? ale time (multiplexed) t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 20 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 20 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 20 ? t advll ale, ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 20 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 20 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 20 ? ale ? address valid time (multiplexed) t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 20 ? ns eacl:sts=1 -20 ? valid address ? rdx time (non-multiplexed) t avrl rdx, a[23:0] ebm:nms= 1 t cyc /2 ? 20 ? ns valid address ? rdx time (multiplexed) t avrl rdx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 20 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 20 ? t advrl rdx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 20 ? ns eacl:ace=1 ebm:nms=0 2t cyc ? 20 ? valid address ? valid data input (non-multiplexed) t avdv a[23:0], ad[15:0] ebm:nms= 1 ? 2t cyc ? 60 ns w/o cycle extension
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 105 valid address ? valid data input (multiplexed) t avdv a[23:16], ad[15:0] eacl:ace=0 ebm:nms=0 ? 3t cyc ? 60 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ? 4t cyc ? 60 t advdv ad[15:0] eacl:ace=0 ebm:nms=0 ? 5t cyc /2 ? 60 ns w/o cycle extension eacl:ace=1 ebm:nms=0 ? 7t cyc /2 ? 60 rdx pulse width t rlrh rdx ? 3t cyc /2 ? 8 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 55 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:0] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 15 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 15 ? valid address ? eclk time t avch a[23:0], eclk ? t cyc ? 20 ? ns t advch ad[15:0], eclk t cyc /2 ? 20 ? rdx ? eclk time t rlch rdx, clk ? t cyc /2 ? 15 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 ? 15 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 55 ns (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 106 2008-2-4 refer to the hardware manual for detailed timing charts. bus timing (write) ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value unit remarks min max valid address ? wrx time (non-multiplexed) t avwl wrx, wrlx, wrhx, a[23:0] eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns eacl:sts=1 ebm:nms=1 t cyc ? 15 ? valid address ? wrx time (multiplexed) t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 15 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 15 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 15 ns eacl:ace=1 ebm:nms=0 2t cyc ? 15 wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 5 ? ns w/o cycle extension a[23:0] ad[15:0] address v il v ih v ih v il read data t rhdx t rldv t advdv eclk t advch 0.8*vcc t rlch ale t lhll t rhlh 0.2*v cc t llax t advll rdx t llrl t rlrh t advrl t avch t avll t avdv t avrl t chdv t axdx
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 107 (t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive = 5ma, c l = 50pf) valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 20 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 15 ? ns wrx ? address valid time (non-multiplexed) t whax wrx, wrlx, wrhx, a[23:0] eacl:sts=1 ebm:nms=1 ? 15 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns wrx ? address valid time (multiplexed) t whax wrx, wrlx, wrhx, a[23:16] ebm:nms=0 t cyc /2 ? 15 ? ns wrx ? ale time (multiplexed) t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 10 ? ns ebm:nms=0 other ebm:ace and eacl:sts setting t cyc ? 10 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 10 ? ns csn ? wrx time (non-multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:sts=0 ebm:nms=1 ? t cyc /2 ? 15 ns eacl:sts=1 ebm:nms=1 ? t cyc ? 15 csn ? wrx time (multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ebm:nms=0 ? 3t cyc /2 ? 15 ns eacl:ace=1 ebm:nms=0 ? 5t cyc /2 ? 15 wrx ? csn time (non-multiplexed) t whcsh wrx, wrlx, wrhx, csn eacl:sts=1 ebm:nms=1 ? 15 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 15 ? ns wrx ? csn time (multiplexed) t whcsh wrx, wrlx, wrhx, csn ebm:nms=0 t cyc /2 ? 15 ? ns parameter symbol pin condition value unit remarks min max valid address ? wrx time (non-multiplexed) t avwl wrx, wrlx, wrhx, a[23:0] eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns eacl:sts=1 ebm:nms=1 t cyc ? 20 ? ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 108 2008-2-4 valid address ? wrx time (multiplexed) t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 ebm:nms=0 3t cyc /2 ? 20 ? ns eacl:ace=1 ebm:nms=0 5t cyc /2 ? 20 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 ebm:nms=0 t cyc ? 20 ns eacl:ace=1 ebm:nms=0 2t cyc ? 20 wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 8 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 25 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 20 ? ns wrx ? address valid time (non-multiplexed) t whax wrx, wrlx, wrhx, a[23:0] eacl:sts=1 ebm:nms=1 ? 20 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns wrx ? address valid time (multiplexed) t whax wrx, wrlx, wrhx, a[23:16] ebm:nms=0 t cyc /2 ? 20 ? ns wrx ? ale time (multiplexed) t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 15 ? ns ebm:nms=0 other ebm:ace and eacl:sts setting t cyc ? 15 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 15 ? ns csn ? wrx time (non-multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:sts=0 ebm:nms=1 ? t cyc /2 ? 20 ns eacl:sts=1 ebm:nms=1 ? t cyc ? 20 csn ? wrx time (multiplexed) t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ebm:nms=0 ? 3t cyc /2 ? 20 ns eacl:ace=1 ebm:nms=0 ? 5t cyc /2 ? 20 wrx ? csn time (non-multiplexed) t whcsh wrx, wrlx, wrhx, csn eacl:sts=1 ebm:nms=1 ? 20 ? ns eacl:sts=0 ebm:nms=1 t cyc /2 ? 20 ? ns wrx ? csn time (multiplexed) t whcsh wrx, wrlx, wrhx, csn ebm:nms=0 t cyc /2 ? 20 ? ns parameter symbol pin condition value unit remarks min max
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 109 refer to the hardware manual for detailed timing charts. ready input timing note : if the rdy setup time is insuf?ient, use the auto-ready function. ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 35 ? ns rdy hold time t ryhh rdy 0 ? ns ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns eclk t wlch 0.8*v cc ale t whlh wrx (wrlx, wrhx) t wlwh t advwl a[23:0] t whax ad[15:0] address write data t dvwh t whdx csn t whcsh t avwl t cslwl 0.2*v cc
preliminary mb96380 series fme-mb96380 rev 8 110 2008-2-4 refer to the hardware manual for detailed timing charts. hold timing refer to the h ardware manual for detailed timing charts. ( t a =? 40 c to + 125 c, v cc = 5.0 v 10 % , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 20 t cyc + 20 ns hakx time ? pin valid time t hahv hakx t cyc ? 20 t cyc +20 ns ( t a =? 40 c to + 125 c, v cc = 3.0 to 4.5v , v ss = 0.0 v , io drive = 5ma, c l = 50pf ) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 25 t cyc +25 ns hakx time ? pin valid time t hahv hakx t cyc ? 25 t cyc +25 ns eclk rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il 0.8*v cc hakx each pin high-z t hahv t xhal 0.8*v cc 0.2*v cc 0.8*v cc 0.2*v cc
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 111 usart timing warning: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in ?b96300 super series hardware manual ? t clkp1 is the cycle time of the peripheral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as follows: if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: (t a = -40?c to 125?c, v cc = 3.0v to 5.5v, v ss = av ss = 0v, io drive = 5ma, c l = 50pf) parameter symbol pin condition v cc =av cc = 4.5v to 5.5v v cc =av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ? 4 t clkp1 ? ns sck sot delay time t slovi sckn, sotn -20 + 20 -30 + 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ? valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ? ns sck valid sin hold time t shixi sckn, sinn 0 ? 0 ? ns serial clock ??pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ? ns serial clock ??pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ? ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ? ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ? ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ...
preliminary mb96380 series fme-mb96380 rev 8 112 2008-2-4 internal shift clock mode sot t slovi sin v il v ih t ivshi v il v ih t shixi t ovshi sck for escr:sces = 0 0.8*v cc t scyci sck for escr:sces = 1 0.8*v cc 0.8*v cc 0.2*v cc 0.2*v cc 0.2*v cc 0.8*v cc 0.2*v cc external shift clock mode t fe v il v il v il v il sot t slove sin v il v ih t ivshe v il v ih t shixe v ih t re v ih t slshe v il v ih t shsle v ih v ih sck for escr:sces = 0 sck for escr:sces = 1 0.8*v cc 0.2*v cc
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 113 i 2 c timing *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat have only to be met if the device does not stretch the ??width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ??width of the scl clock t low 4.7 ? 1.3 ? s ??width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto
preliminary mb96380 series fme-mb96380 rev 8 114 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 115 5. analog digital converter note: the accuracy gets worse as |avrh - avrl| becomes smaller. de?ition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. t otal error : difference between the actual value and the ideal value. the total error includes zero transition error, full-scale transition error and linear error. (t a = -40 ?c to +125 ?c, 3.0 v avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - -3 - +3 lsb nonlinearity error - - -2.5 - +2.5 lsb differential nonlinearity error - - -1.9 - +1.9 lsb zero reading voltage v ot ann avrl - 1.5 avrl+ 0.5 avrl + 2.5 lsb full scale reading voltage v fst ann avrh - 3.5 avrh - 1.5 avrh + 0.5 lsb compare time - - 1.0 - 16,500 s 4.5v v cc 5.5v 2.0 - - s 3.0v v cc < 4.5v sampling time - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 3.0v v cc < 4.5v analog port input cur- rent i ain ann -1 - +1 at a = 25 ?c -3 - +3 at a = 125 ?c analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrhav rh2 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma ad converter ac- tive i ah avcc - - 5 a ad converter not operated reference voltage cur- rent i r avrh/ avrl - 0.7 1 ma ad converter ac- tive i rh avrh/ avrl --5 a ad converter not operated offset between input channels - ann - - tbd lsb
preliminary mb96380 series fme-mb96380 rev 8 116 2008-2-4 non l inear ity error : deviation between a line across zero-transition line (?0 0000 0000 <--> ?0 0000 0001? and full-scale transition line (?1 1111 1110?<--> ?1 1111 1111? and actual conversion characteristics. diff erential linear ity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. z ero reading v oltage: input voltage which results in the minimum conversion value. full scale reading v oltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output ? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error n: a/d converter digital output value
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 117 notes on a/d converter section about the external impedance of the analog input and the sampling time of the a/d converter (with sample and hold circuit): if the external impedance is too high to keep suf?ient sampling time, the analog voltage charged to the internal sample and hold capacitor is insuf?ient, adversely affecting a/d conversion precision. 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error differential linearity error differential linearity error of digital output n = 1 lsb = analog input circuit model: comparator sampling switch r c analog input reference value: c = 8.5 pf (max) non linearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] n : a/d converter digital output value v ot : voltage at which digital output transits from ?00 h ?to ?01 h . v fst : voltage at which digital output transits from ?fe h ?to ?ff h .
preliminary mb96380 series fme-mb96380 rev 8 118 2008-2-4 to satisfy the a/d conversion precision standard, the relationship between the external impedance and minimum sampling time must be considered and then either the resistor value and operating frequency must be adjusted or the external impedance must be decreased so that the sampling time (t samp ) is longer than the minimum value. usually, this value is set to 7 , where = rc. if the external input resistance (r ext ) connected to the analog input is included, the sampling time is expressed as follows: t samp [min] = 7 (r ext + 2.6k ? ) c for 4.5 av cc 5.5 t samp [min] = 7 (r ext + 12.1k ? ) c for 3.0 av cc 4.5 if the sampling time cannot be suf?ient, connect a capacitor of about 0.1 f to the analog input pin. about the error the accuracy gets worse as |avrh - avrl| becomes smaller.
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 119 6. alarm comparator (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power supply current i a5almf av cc -2540 a alarm comparator enabled in fast mode (one channel) i a5alms -710 a alarm comparator enabled in slow mode (one channel) i a5almh --5 a alarm comparator disabled alarm pin input cur- rent i alin alarm0, alarm1 -1 - +1 at a = 25 ?c -3 - +3 at a = 125 ?c alarm pin input volt- age range v alin 0-av cc v external low threshold high->low transition v evtl(h->l) 0.36 * av cc -0.25 0.36 * av cc -0.1 v intref = 0 external low threshold low->high transition v evtl(l->h) 0.36 * av cc +0.1 0.36 * av cc +0.25 v external high threshold high->low transition v evth(h->l) 0.78 * av cc -0.25 0.78 * av cc -0.1 v external high threshold low->high transition v evth(l->h) 0.78 * av cc +0.1 0.78 * av cc +0.25 v internal low threshold high->low transition v ivtl(h->l) 0.9 1.1 - v intref = 1 internal low threshold low->high transition v ivtl(l->h) - 1.3 1.55 v internal high threshold high->low transition v ivth(h->l) 2.2 2.4 - v internal high threshold low->high transition v ivth(l->h) - 2.6 2.85 v switching hysteresis v hys 50 - 300 mv comparison time t compf - 0.3 2 s cmd = 1 (fast) t comps - 2 100 s cmd = 0 (slow)
preliminary mb96380 series fme-mb96380 rev 8 120 2008-2-4 comparator output v xvtx(l->h) v hys v alin h l v xvtx(h->l)
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 121 7. low voltage detector characteristics levels 10 to 15 are not used in this device. for correct detection, the slope of the voltage level must satisfy . faster variations are regarded as noise and may not be detected. the functional operation of the mcu is guaranteed down to the minimum low voltage detection level of vcc = 2.7v. the electrical characteristics however are only valid in the speci?d range (usually down to 3.0v). (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol value unit remarks min max stabilization time t lvdstab 60 75 s level 0 v dl0 2.7 2.9 v cilcr:lvl[3:0]=?000 level 1 v dl1 2.9 3.1 v cilcr:lvl[3:0]=?001 level 2 v dl2 3.1 3.3 v cilcr:lvl[3:0]=?010 level 3 v dl3 3.5 3.75 v cilcr:lvl[3:0]=?011 level 4 v dl4 3.6 3.85 v cilcr:lvl[3:0]=?100 level 5 v dl5 3.7 3.95 v cilcr:lvl[3:0]=?101 level 6 v dl6 3.8 4.05 v cilcr:lvl[3:0]=?110 level 7 v dl7 3.9 4.15 v cilcr:lvl[3:0]=?111 level 8 v dl8 4.0 4.25 v cilcr:lvl[3:0]=?000 level 9 v dl9 4.1 4.35 v cilcr:lvl[3:0]=?001 level 10 v dl10 not used level 11 v dl11 not used level 12 v dl12 not used level 13 v dl13 not used level 14 v dl14 not used level 15 v dl15 not used t d d v 0.004 v s -----
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 122 low voltage detector operation in the following ?ure, the occurrence of a low voltage condition is illustrated. for a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. voltage [v] time [s] v cc v dlx, min v dlx, max dv dt low voltage reset assertion normal operation power reset extension time
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 123 8. flash memory program/erase characteristics *1: this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to convert high temperature measurements into normalized value at 85 o c) ( t a = 25 o c , v cc = 5.0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s erasure programming time not included chip erase time - n*0.9 n*3.6 s n is the number of flash sector of the device word (16-bit width) pro- gramming time - 23 370 us system overhead time not in- cluded programme/erase cycle 10 000 cycle flash data retention time 20 year *1
preliminary mb96380 series fme-mb96380 rev 8 124 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 125 example characteristics the diagrams below show the characteristics of one measured sample with typical process parameters. run mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (2 mhz) rc clock (100 khz) sub osc.(32 khz) pll clock (56 mhz) sleep mode 0.01 0.10 1.00 10.00 100.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc.(32 khz) rc clock (2 mhz) pll clock (56 mhz)
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 126 timer mode 0.01 0.10 1.00 10.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma] main osc. (4 mhz) rc clock (100 khz) sub osc. (32 khz) pll clock (56 mhz) rc clock (2 mhz) stop mode 0.00 0.01 0.10 1.00 -50.00 0.00 50.00 100.00 150.00 ta [?] icc [ma]
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 127 used settings mode selected source clock clock/regulator settings run mode pll clks1 = clks2 = clkb = clkp1 = 56 mhz clkp2 = 28 mhz regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4 mhz regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2 mhz regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100 khz regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 32 khz regulator in low power mode a core voltage = 1.8 v sleep mode pll clks1 = clks2 = clkp1 = 56 mhz clkp2 = 28 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.9 v main osc. clks1 = clks2 = clkp1 = clkp2 = 4 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2 mhz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100 khz (clkb is stopped in this mode) regulator in high power mode core voltage = 1.8 v sub osc. clks1 = clks2 = clkp1 = clkp2 = 32 khz (clkb is stopped in this mode) regulator in low power mode a core voltage = 1.8 v
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 128 timer mode pll clkmc = 4 mhz, clkpll = 56 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.9 v main osc. clkmc = 4 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock fast clkrc = 2 mhz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v rc clock slow clkrc = 100 khz (system clocks are stopped in this mode) regulator in high power mode, core voltage = 1.8 v sub osc. clksc = 100 khz (system clocks are stopped in this mode) regulator in low power mode a, core voltage = 1.8 v stop mode stopped (all clocks are stopped in this mode) regulator in low power mode b, core voltage = 1.8 v used settings mode selected source clock clock/regulator settings
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 129 package dimension mb96(f)38x lqfp 120p 120-pin plastic lqfp lead pitch 0.50 mm package width package length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max weight 0.88 g code (reference) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt-120p-m21) (fpt-120p-m21) c 2002 fujitsu limited f120033s-c-4-4 1 30 60 31 90 61 120 91 sq 18.00?.20(.709?008)sq 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) index .006 ?001 +.002 ?.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?004 +.008 ?.10 +0.20 1.50 details of "a" part (mounting height) 0.60?.15 (.024?006) 0.25(.010) (.004?002) 0.10?.05 (stand off) 0~8 ? * .630 ?004 +.016 ?.10 +0.40 16.00 dimensions in mm (inches). note: the values in parentheses are reference values.
preliminary mb96380 series fme-mb96380 rev 8 130 2008-2-4
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 131 ordering information *1: these devices are under development. all information in this datasheet is preliminary for the devices under development. part number independent 32kb data flash subclock persistent low volt- age reset package remarks mb96384ysa pmc-gse2 *1 no no yes 120 pin plastic lqfp (fpt-120p-m21) mb96384rsa pmc-gse2 *1 no mb96384ywa pmc-gse2 *1 yes yes mb96384rwa pmc-gse2 *1 no mb96385ysa pmc-gse2 *1 no yes mb96385rsa pmc-gse2 *1 no mb96385ywa pmc-gse2 *1 yes yes mb96385rwa pmc-gse2 *1 no mb96f385ysa pmc-gse2 *1 no yes mb96f385rsa pmc-gse2 *1 no mb96f385ywa pmc-gse2 *1 yes yes mb96f385rwa pmc-gse2 *1 no mb96f386ysb pmc-gse2 no no yes 120 pin plastic lqfp (fpt-120p-m21) mb96f386rsb pmc-gse2 no mb96f386ywb pmc-gse2 yes yes mb96f386rwb pmc-gse2 no mb96f387ysb pmc-gse2 no yes mb96f387rsb pmc-gse2 no mb96f387ywb pmc-gse2 yes yes mb96f387rwb pmc-gse2 no mb96f388tsa pmc-gse2 *1 yes no yes mb96f388hsa pmc-gse2 *1 no mb96f388twa pmc-gse2 *1 yes yes mb96f388hwa pmc-gse2 *1 no mb96f389ysa pmc-gse2 *1 no (flash b size 288kb) no yes mb96f389rsa pmc-gse2 *1 no mb96f389ywa pmc-gse2 *1 yes yes mb96f389rwa pmc-gse2 *1 no mb96v300brb-es emulated by ext. ram yes no 416 pin plastic bga (bga416-m02) for evalua- tion
preliminary mb96380 series fme-mb96380 rev 8 132 2008-2-4 this datasheet is also valid for the following outdated devices: mb96f386ysa, mb96f386rsa, mb96f386ywa, mb96f386rwa, mb96f387ysa, mb96f387rsa, mb96f387ywa, mb96f387rwa
preliminary mb96380 series fme-mb96380 rev 8 2008-2-4 133 revision history revision date modi?ation prelim 1 2007-05-2 creation prelim 2 2007-05-24 electrical characteristics and memory description updates prelim 3 2007-08-09 typo errors corrections, flash memory programming interface update prelim 4 2007-08-31 update of dc characteristics. new 388 and 389 added. lvd chapter added as well as an example characteristics chapter prelim 5 2007-09-06 updates of the dc characteristics, interrupt vector table update, update of the lvd characteristics prelim 6 2007-11-14 memory map for external bus modi?d. modi?ations of the drawing of the pin circuits. electrical characteristics updates. rephrasing and typos corrections. add slew rate high current outputs chapter. modi?ation of the block diagram. memory map modi?d for flash. ram memory map added. pin circuit type corrected. type l io is now included. prelim 7 2007-12-12 memory io map modi?d new flash/rom con?uration presentation ordering information: mb96300b used as reference. block diagram modi?d to included relocated pins. main flash becomes flash memory a and satellite ?sh becomes flash memory b
preliminary mb96380 series fme-mb96380 rev 8 134 2008-2-4 prelim 8 2008-02-04 devices under development added: mb96384/385/f385/f388/f389 block diagram corrected (existing resource pins) pin assignment: ttg8 -> ttg7 pin function table corrected i/o circuit type diagrams corrected memory map cleaned up "flash sector con?uration" replaced by corrected "user rom memory map for flash devices", ?om con?uration replaced by ?ser rom memory map for mask rom devices io map table regenerated: - port register: naming style corrected - memory control registers renamed (main/sat -> a/b) - addresses after 000bffh removed absolute maximum ratings: pd and ta speci?d more precisely run and sleep mode currents: more conditions added (1ws settings) run mode current spec in 48/24mhz mode corrected maximum clkp2 frequency for mb96f386/f387 corrected high current port input capacitance added external bus timings: missing conditions added and readability improved alarm comparator spec updated (transition voltages de?ed) mb96v300a removed ordering information updated typos and formatting corrected revision date modi?ation
preliminary mb96380 series fme-mb96380 rev 8
preliminary mb96380 series fme-mb96380 rev 8 fujitsu limited all rights reserved. the contents of this document are subject to change without no- tice. customers are advised to consult with fujitsu sales repre- sentatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the pur- pose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper op- eration of the device with respect to use based on such informa- tion. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of func- tion and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, per- sonal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support sys- tem, missile launch control in weapon system), or (2) for use re- quiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior au- thorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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